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This commit is contained in:
Hansung Kim
2024-06-09 13:39:53 -07:00
parent 3e4a04351b
commit 3254ac3741
2 changed files with 5 additions and 4 deletions
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3
src/main/scala/radiance/memory/VortexCache.scala
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@@ -129,7 +129,8 @@ class VortexBankPassThrough(config: VortexL1Config)(implicit p: Parameters)
// println(s"${upstream.params.sourceBits} <= ${downstream.params.sourceBits}") // println(s"${upstream.params.sourceBits} <= ${downstream.params.sourceBits}")
require(upstream.params.sourceBits <= downstream.params.sourceBits, require(upstream.params.sourceBits <= downstream.params.sourceBits,
"mem-side source of L1 cache truncates core-side source! " + "mem-side source of L1 cache truncates core-side source! " +
"Try lowering core or coalescer srcIds") "Try lowering core/coalescer srcIds, or increasing sourceWidth " +
"for VortexBankPassThrough")
downstream.a <> upstream.a downstream.a <> upstream.a
upstream.d <> downstream.d upstream.d <> downstream.d

6
src/main/scala/radiance/subsystem/Configs.scala
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@@ -172,7 +172,7 @@ class WithRadianceCluster(
case PossibleTileLocations => up(PossibleTileLocations) :+ InCluster(clusterId) case PossibleTileLocations => up(PossibleTileLocations) :+ InCluster(clusterId)
}) })
// `nSrcIds`: number of source IDs for dmem requests on each SIMT lane // `nSrcIds`: number of source IDs for each mem lane. This is for all warps
class WithSimtConfig(nWarps: Int = 4, nCoreLanes: Int = 4, nMemLanes: Int = 4, nSrcIds: Int = 8) class WithSimtConfig(nWarps: Int = 4, nCoreLanes: Int = 4, nMemLanes: Int = 4, nSrcIds: Int = 8)
extends Config((site, _, up) => { extends Config((site, _, up) => {
case SIMTCoreKey => { case SIMTCoreKey => {
@@ -206,8 +206,8 @@ class WithVortexL1Banks(nBanks: Int = 4) extends Config ((site, here, up) => {
case VortexL1Key => { case VortexL1Key => {
Some(defaultVortexL1Config.copy( Some(defaultVortexL1Config.copy(
numBanks = nBanks, numBanks = nBanks,
inputSize = up(SIMTCoreKey).get.nMemLanes * 4, inputSize = up(SIMTCoreKey).get.nMemLanes * 4/*32b word*/,
cacheLineSize = up(SIMTCoreKey).get.nMemLanes * 4, cacheLineSize = up(SIMTCoreKey).get.nMemLanes * 4/*32b word*/,
memSideSourceIds = 16, memSideSourceIds = 16,
mshrSize = 16, mshrSize = 16,
)) ))