diff --git a/src/main/scala/radiance/memory/VortexCache.scala b/src/main/scala/radiance/memory/VortexCache.scala
index f1eb158..b592afd 100644
--- a/src/main/scala/radiance/memory/VortexCache.scala
+++ b/src/main/scala/radiance/memory/VortexCache.scala
@@ -129,7 +129,8 @@ class VortexBankPassThrough(config: VortexL1Config)(implicit p: Parameters)
     // println(s"${upstream.params.sourceBits} <= ${downstream.params.sourceBits}")
     require(upstream.params.sourceBits <= downstream.params.sourceBits,
             "mem-side source of L1 cache truncates core-side source! " +
-            "Try lowering core or coalescer srcIds")
+            "Try lowering core/coalescer srcIds, or increasing sourceWidth " +
+            "for VortexBankPassThrough")
 
     downstream.a <> upstream.a
     upstream.d <> downstream.d
diff --git a/src/main/scala/radiance/subsystem/Configs.scala b/src/main/scala/radiance/subsystem/Configs.scala
index 1161f35..2fc963b 100644
--- a/src/main/scala/radiance/subsystem/Configs.scala
+++ b/src/main/scala/radiance/subsystem/Configs.scala
@@ -172,7 +172,7 @@ class WithRadianceCluster(
   case PossibleTileLocations => up(PossibleTileLocations) :+ InCluster(clusterId)
 })
 
-// `nSrcIds`: number of source IDs for dmem requests on each SIMT lane
+// `nSrcIds`: number of source IDs for each mem lane.  This is for all warps
 class WithSimtConfig(nWarps: Int = 4, nCoreLanes: Int = 4, nMemLanes: Int = 4, nSrcIds: Int = 8)
 extends Config((site, _, up) => {
   case SIMTCoreKey => {
@@ -206,8 +206,8 @@ class WithVortexL1Banks(nBanks: Int = 4) extends Config ((site, here, up) => {
   case VortexL1Key => {
     Some(defaultVortexL1Config.copy(
       numBanks = nBanks,
-      inputSize = up(SIMTCoreKey).get.nMemLanes * 4,
-      cacheLineSize = up(SIMTCoreKey).get.nMemLanes * 4,
+      inputSize = up(SIMTCoreKey).get.nMemLanes * 4/*32b word*/,
+      cacheLineSize = up(SIMTCoreKey).get.nMemLanes * 4/*32b word*/,
       memSideSourceIds = 16,
       mshrSize = 16,
     ))