Rename VortexTile -> RadianceTile

src/main/scala/radiance/subsystem/Configs.scala

@@ -18,7 +18,7 @@ class WithRadianceCores(
   case TilesLocated(InSubsystem) => {
     val prev = up(TilesLocated(InSubsystem), site)
     val idOffset = prev.size
-    val vortex = VortexTileParams(
+    val vortex = RadianceTileParams(
       core = VortexCoreParams(fpu = None),
       btb = None,
       useVxCache = useVxCache,
@@ -41,7 +41,7 @@ class WithRadianceCores(
         nTLBBasePageSectors = 1,
         nTLBSuperpages = 1,
         blockBytes = site(CacheBlockBytes))))
-    List.tabulate(n)(i => VortexTileAttachParams(
+    List.tabulate(n)(i => RadianceTileAttachParams(
       vortex.copy(tileId = i + idOffset),
       RocketCrossingParams()
     )) ++ prev

src/main/scala/radiance/subsystem/RadianceSubsystem.scala

@@ -5,7 +5,7 @@ package radiance.subsystem
 import freechips.rocketchip.subsystem._
 import radiance.tile._
 
-case class VortexTileAttachParams(
+case class RadianceTileAttachParams(
-  tileParams: VortexTileParams,
+  tileParams: RadianceTileParams,
   crossingParams: RocketCrossingParams
-) extends CanAttachTile { type TileType = VortexTile }
+) extends CanAttachTile { type TileType = RadianceTile }

src/main/scala/radiance/tile/RadianceTile.scala

@@ -20,7 +20,7 @@ import radiance.memory._
 import gemmini.{Gemmini, GemminiCustomConfigs}
 import radiance.subsystem.{GPUMemParams, GPUMemory}
 
-case class VortexTileParams(
+case class RadianceTileParams(
     core: VortexCoreParams = VortexCoreParams(),
     useVxCache: Boolean = false,
     icache: Option[ICacheParams] = None /* Some(ICacheParams()) */,
@@ -33,22 +33,22 @@ case class VortexTileParams(
     blockerCtrlAddr: Option[BigInt] = None,
     clockSinkParams: ClockSinkParameters = ClockSinkParameters(),
     boundaryBuffers: Option[RocketTileBoundaryBufferParams] = None
-) extends InstantiableTileParams[VortexTile] {
+) extends InstantiableTileParams[RadianceTile] {
   // TODO: want to use ICache/DCacheParams as well
   // require(icache.isDefined)
   // require(dcache.isDefined)
 
   def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(
       implicit p: Parameters
-  ): VortexTile = {
+  ): RadianceTile = {
-    new VortexTile(this, crossing, lookup)
+    new RadianceTile(this, crossing, lookup)
   }
   val baseName = name.getOrElse("radiance_tile")
   val uniqueName = s"${baseName}_$tileId"
 }
 
 // TODO: move to VortexCore
-// VortexTileParams extends TileParams which require a `core: CoreParams`
+// RadianceTileParams extends TileParams which require a `core: CoreParams`
 // field, so VortexCoreParams needs to extend from CoreParams as well,
 // requiring all these fields to be initialized.  Most of this is unnecessary
 // though. TODO see how BOOM does that
@@ -102,8 +102,8 @@ case class VortexCoreParams(
   val traceHasWdata: Boolean = false // ooo wb, so no wdata in trace
 }
 
-class VortexTile private (
+class RadianceTile private (
-    val vortexParams: VortexTileParams,
+    val vortexParams: RadianceTileParams,
     crossing: ClockCrossingType,
     lookup: LookupByHartIdImpl,
     q: Parameters
@@ -112,7 +112,7 @@ class VortexTile private (
     with SourcesExternalNotifications {
   // Private constructor ensures altered LazyModule.p is used implicitly
   def this(
-      params: VortexTileParams,
+      params: RadianceTileParams,
       crossing: HierarchicalElementCrossingParamsLike,
       lookup: LookupByHartIdImpl
   )(implicit p: Parameters) =
@@ -137,7 +137,7 @@ class VortexTile private (
 
   require(
     p(SIMTCoreKey).isDefined,
-    "SIMTCoreKey not defined; make sure to use WithSimtLanes when using VortexTile"
+    "SIMTCoreKey not defined; make sure to use WithSimtLanes when using RadianceTile"
   )
   val numLanes = p(SIMTCoreKey) match {
     case Some(simtParam) => simtParam.nLanes
@@ -410,7 +410,7 @@ class VortexTile private (
     Resource(cpuDevice, "reg").bind(ResourceAddress(tileId))
   }
 
-  override lazy val module = new VortexTileModuleImp(this)
+  override lazy val module = new RadianceTileModuleImp(this)
 
   override def makeMasterBoundaryBuffers(
       crossing: ClockCrossingType
@@ -443,7 +443,7 @@ class VortexTile private (
   }
 }
 
-class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
+class RadianceTileModuleImp(outer: RadianceTile) extends BaseTileModuleImp(outer) {
   Annotated.params(this, outer.vortexParams)
 
   val core = Module(new Vortex(outer)(outer.p))

src/main/scala/radiance/tile/VortexCore.scala

@@ -33,7 +33,7 @@ class VortexBundleD(
   val data = UInt(dataWidth.W) // FIXME: hardcoded
 }
 
-class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle {
+class VortexBundle(tile: RadianceTile)(implicit p: Parameters) extends CoreBundle {
   val clock = Input(Clock())
   val reset = Input(Reset())
   // val hartid = Input(UInt(tileIdLen.W))
@@ -105,7 +105,7 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
   val traceStall = Input(Bool())
 }
 
-class Vortex(tile: VortexTile)(implicit p: Parameters)
+class Vortex(tile: RadianceTile)(implicit p: Parameters)
     extends BlackBox(
       // Each Vortex core gets tied-off tileId of 0, 1, 2, 3, ...
       // The actual MHARTID read by the program is different by warp, not core;