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Connect CoalShiftQueue enq.ready to upstream TL.ready

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Now CoalShiftQueue can properly stall memtrace driver.
This commit is contained in:
Hansung Kim
2023-05-08 14:27:54 -07:00
parent 8cdbc81bdd
commit 2e219ea15a
1 changed files with 4 additions and 1 deletions
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5
src/main/scala/tilelink/Coalescing.scala
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@@ -604,7 +604,10 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
val deq = reqQueues.io.queue.deq(lane) val deq = reqQueues.io.queue.deq(lane)
enq.valid := tlIn.a.valid enq.valid := tlIn.a.valid
enq.bits := req enq.bits := req
deq.ready := true.B // TODO: deq.ready should respect downstream arbiter // TODO: deq.ready should respect downstream arbiter
deq.ready := true.B
// Stall upstream core or memtrace driver when shiftqueue is not ready
tlIn.a.ready := enq.ready
tlOut.a.valid := deq.valid tlOut.a.valid := deq.valid
tlOut.a.bits := deq.bits.toTLA(edgeOut) tlOut.a.bits := deq.bits.toTLA(edgeOut)