From 2e219ea15a6627a8532ce1daa84a715e28776d63 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 8 May 2023 14:27:54 -0700 Subject: [PATCH] Connect CoalShiftQueue enq.ready to upstream TL.ready Now CoalShiftQueue can properly stall memtrace driver. --- src/main/scala/tilelink/Coalescing.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 0addef1..4b4a0f6 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -604,7 +604,10 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends val deq = reqQueues.io.queue.deq(lane) enq.valid := tlIn.a.valid enq.bits := req - deq.ready := true.B // TODO: deq.ready should respect downstream arbiter + // TODO: deq.ready should respect downstream arbiter + deq.ready := true.B + // Stall upstream core or memtrace driver when shiftqueue is not ready + tlIn.a.ready := enq.ready tlOut.a.valid := deq.valid tlOut.a.bits := deq.bits.toTLA(edgeOut)