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This commit is contained in:
Hansung Kim
2023-04-17 21:31:13 -07:00
parent 334d05b222
commit 2ac5ee398a
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/tilelink/Coalescing.scala
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@@ -204,9 +204,10 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule
val (tlCoal, edgeCoal) = outer.coalescerNode.out(0)
val coalReqAddress = Wire(UInt(tlCoal.params.addressBits.W))
// TODO: bogus address
// FIXME: bogus address
coalReqAddress := (0xabcd.U + coalSourceId) << 4
// FIXME: coalesce lane 0 and lane 2's queue head whenever they're valid
// FIXME: bogus coalescing logic: coalesce whenever all 4 lanes have valid
// queue head
coalReqValid := reqQueues(0).io.deq.valid && reqQueues(1).io.deq.valid &&
reqQueues(2).io.deq.valid && reqQueues(3).io.deq.valid
when(coalReqValid) {