From 2ac5ee398a5e7d3fe172ec88929f3f7a77b645a2 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Mon, 17 Apr 2023 21:31:13 -0700 Subject: [PATCH] Doc --- src/main/scala/tilelink/Coalescing.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 2afcae8..525cf32 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -204,9 +204,10 @@ class CoalescingUnitImp(outer: CoalescingUnit, numLanes: Int) extends LazyModule val (tlCoal, edgeCoal) = outer.coalescerNode.out(0) val coalReqAddress = Wire(UInt(tlCoal.params.addressBits.W)) - // TODO: bogus address + // FIXME: bogus address coalReqAddress := (0xabcd.U + coalSourceId) << 4 - // FIXME: coalesce lane 0 and lane 2's queue head whenever they're valid + // FIXME: bogus coalescing logic: coalesce whenever all 4 lanes have valid + // queue head coalReqValid := reqQueues(0).io.deq.valid && reqQueues(1).io.deq.valid && reqQueues(2).io.deq.valid && reqQueues(3).io.deq.valid when(coalReqValid) {