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Enable rs1/2/3 duplicated GPR by default

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This commit is contained in:
Hansung Kim
2024-04-15 21:46:43 -07:00
parent 824cae7c50
commit 1aa2d93600
2 changed files with 6 additions and 4 deletions
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7
radiance.mk
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@@ -2,19 +2,20 @@
# extra variables/targets ingested by the chipyard make system
##############################################################
RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
##################################################################
# THE FOLLOWING MUST BE += operators
##################################################################
RADPIE_SRC_DIR = $(base_dir)/generators/radiance/radpie
RADPIE_BUILD_DIR = $(RADPIE_SRC_DIR)/target/release
# EXTRA_SIM_REQS += radpie
EXTRA_SIM_LDFLAGS += -L$(RADPIE_BUILD_DIR) -Wl,-rpath,$(RADPIE_BUILD_DIR) -lradpie
EXTRA_SIM_PREPROC_DEFINES += \
+define+SIMULATION \
+define+SV_DPI \
+define+GPR_RESET \
+define+GPR_DUPLICATED \
+define+LSU_DUP_DISABLE \
+define+DBG_TRACE_CORE_PIPELINE_VCS \
+define+PERF_ENABLE \

3
src/main/scala/radiance/tile/VortexCore.scala
View File

@@ -175,7 +175,8 @@ class Vortex(tile: RadianceTile)(implicit p: Parameters)
addResource("/vsrc/vortex/hw/rtl/core/VX_issue.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_lsu_unit.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_muldiv_unit.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_operands.sv")
// addResource("/vsrc/vortex/hw/rtl/core/VX_operands.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_operands_dup.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_pending_instr.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_schedule.sv")
addResource("/vsrc/vortex/hw/rtl/core/VX_scoreboard.sv")