Rename core.io.cease to finished; bump vortex
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Submodule src/main/resources/vsrc/vortex updated: c9d1275f0e...4643edf3e9
@@ -100,7 +100,7 @@ class VortexBundle(tile: VortexTile)(implicit p: Parameters) extends CoreBundle
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//val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
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//val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
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//val trace = Output(new TraceBundle)
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//val trace = Output(new TraceBundle)
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//val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))
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//val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))
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val cease = Output(Bool())
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val finished = Output(Bool())
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val wfi = Output(Bool())
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val wfi = Output(Bool())
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val traceStall = Input(Bool())
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val traceStall = Input(Bool())
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}
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}
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@@ -451,11 +451,11 @@ class VortexTileModuleImp(outer: VortexTile) extends BaseTileModuleImp(outer) {
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core.io.reset_vector := DontCare
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core.io.reset_vector := DontCare
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outer.regNode.regmap(
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outer.regNode.regmap(
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0x00 -> Seq(RegField.r(32, core.io.cease))
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0x00 -> Seq(RegField.r(32, core.io.finished))
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)
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)
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// Report when the tile has ceased to retire instructions; for now the only cause is clock gating
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// Report when the tile has ceased to retire instructions
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outer.reportCease(outer.vortexParams.core.clockGate.option(core.io.cease))
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outer.reportCease(Some(core.io.finished))
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outer.reportWFI(Some(core.io.wfi))
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outer.reportWFI(Some(core.io.wfi))
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