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Merge remote-tracking branch 'origin/graphics' into local-dev-branch

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Vamber Yang
2023-05-05 19:00:21 -07:00
parent 3dad961082 4ebcfbb9eb
commit 124e974969
3 changed files with 5 additions and 6 deletions
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6
src/main/scala/tilelink/Coalescing.scala
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@@ -5,7 +5,7 @@ package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.ChiselEnum
import freechips.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
// import freechips.rocketchip.devices.tilelink.TLTestRAM
import freechips.rocketchip.util.MultiPortQueue
@@ -251,8 +251,7 @@ class CoalShiftQueue[T <: Data](gen: T, entries: Int, config: CoalescerConfig) e
// dequeue is valid when:
// head entry is valid, has not been processed by downstream, and is not coalescable
deq.bits := elts.map(_.head.bits)(i)
deq.valid := elts.map(_.head.valid)(i) && !deqDone(i) &&
(!io.invalidate.valid || !io.coalescable(i))
deq.valid := elts.map(_.head.valid)(i) && !deqDone(i) && !io.coalescable(i)
// can take new entries if not empty, or if full but shifting
enq.ready := (!ctrl.full) || ctrl.shift
@@ -550,6 +549,7 @@ class MultiCoalescer(windowT: CoalShiftQueue[ReqQueueEntry], coalReqT: ReqQueueE
def disable = {
io.coalReq.valid := false.B
io.invalidate.valid := false.B
io.coalescable.foreach { _ := false.B }
}
if (!config.enable) disable
}

3
src/main/scala/tilelink/TracerSystemMem.scala
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@@ -3,10 +3,9 @@ package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
import freechips.rocketchip.config.{Parameters, Field, Config}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
// class class, consumed by WithGPUTacer config and GPUTracerKey

2
src/test/scala/coalescing/CoalescingUnitTest.scala
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@@ -6,7 +6,7 @@ import org.scalatest.flatspec.AnyFlatSpec
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util.MultiPortQueue
import freechips.rocketchip.diplomacy._
import chipsalliance.rocketchip.config.Parameters
import org.chipsalliance.cde.config.Parameters
import chisel3.util.{DecoupledIO, Valid}
import chisel3.util.experimental.BoringUtils