From 42b03edbf744f3d02b586d830d7da52cc9e71aea Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 5 May 2023 14:50:25 -0700 Subject: [PATCH 1/2] Update import path to cde to reflect upstream changes --- src/main/scala/tilelink/Coalescing.scala | 2 +- src/main/scala/tilelink/TracerSystemMem.scala | 3 +-- src/test/scala/coalescing/CoalescingUnitTest.scala | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index f967a60..7aff976 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -5,7 +5,7 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.ChiselEnum -import freechips.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ // import freechips.rocketchip.devices.tilelink.TLTestRAM import freechips.rocketchip.util.MultiPortQueue diff --git a/src/main/scala/tilelink/TracerSystemMem.scala b/src/main/scala/tilelink/TracerSystemMem.scala index 0b099c8..e0d495b 100644 --- a/src/main/scala/tilelink/TracerSystemMem.scala +++ b/src/main/scala/tilelink/TracerSystemMem.scala @@ -3,10 +3,9 @@ package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ -import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes} -import freechips.rocketchip.config.{Parameters, Field, Config} +import org.chipsalliance.cde.config.{Parameters, Field, Config} // class class, consumed by WithGPUTacer config and GPUTracerKey diff --git a/src/test/scala/coalescing/CoalescingUnitTest.scala b/src/test/scala/coalescing/CoalescingUnitTest.scala index 585d412..4d6c346 100644 --- a/src/test/scala/coalescing/CoalescingUnitTest.scala +++ b/src/test/scala/coalescing/CoalescingUnitTest.scala @@ -6,7 +6,7 @@ import org.scalatest.flatspec.AnyFlatSpec import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.MultiPortQueue import freechips.rocketchip.diplomacy._ -import chipsalliance.rocketchip.config.Parameters +import org.chipsalliance.cde.config.Parameters import chisel3.util.{DecoupledIO, Valid} import chisel3.util.experimental.BoringUtils From 4ebcfbb9ebb569963117f6a748a951697d2bd1ae Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 5 May 2023 15:51:59 -0700 Subject: [PATCH 2/2] Revert deq.valid; force-set io.coalesceable instead for coal.enable --- src/main/scala/tilelink/Coalescing.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/tilelink/Coalescing.scala b/src/main/scala/tilelink/Coalescing.scala index 7aff976..52f6c5b 100644 --- a/src/main/scala/tilelink/Coalescing.scala +++ b/src/main/scala/tilelink/Coalescing.scala @@ -247,8 +247,7 @@ class CoalShiftQueue[T <: Data](gen: T, entries: Int, config: CoalescerConfig) e // dequeue is valid when: // head entry is valid, has not been processed by downstream, and is not coalescable deq.bits := elts.map(_.head.bits)(i) - deq.valid := elts.map(_.head.valid)(i) && !deqDone(i) && - (!io.invalidate.valid || !io.coalescable(i)) + deq.valid := elts.map(_.head.valid)(i) && !deqDone(i) && !io.coalescable(i) // can take new entries if not empty, or if full but shifting enq.ready := (!ctrl.full) || ctrl.shift @@ -546,6 +545,7 @@ class MultiCoalescer(windowT: CoalShiftQueue[ReqQueueEntry], coalReqT: ReqQueueE def disable = { io.coalReq.valid := false.B io.invalidate.valid := false.B + io.coalescable.foreach { _ := false.B } } if (!config.enable) disable }