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kernels/hw/rtl/interfaces
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Blaise Tine c6afc35989 adding data fence support
2021-06-28 06:12:18 -07:00
..
VX_alu_req_if.v
rename use_imm and use_PC
2021-03-01 00:38:46 -08:00
VX_branch_ctl_if.v
pipeline refactoring - fmax >= 222 mhz
2020-08-14 21:50:14 -07:00
VX_cache_mem_req_if.v
refactoring cache_config
2021-05-27 14:41:46 -07:00
VX_cache_mem_rsp_if.v
refactoring cache_config
2021-05-27 14:41:46 -07:00
VX_cmt_to_csr_if.v
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
VX_commit_if.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
VX_csr_req_if.v
csr minor update
2021-03-08 03:46:07 -08:00
VX_dcache_core_req_if.v
refactoring cache_config
2021-05-27 14:41:46 -07:00
VX_dcache_core_rsp_if.v
refactoring cache_config
2021-05-27 14:41:46 -07:00
VX_decode_if.v
rename use_imm and use_PC
2021-03-01 00:38:46 -08:00
VX_fpu_req_if.v
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
VX_fpu_to_csr_if.v
tabs cleanup
2020-11-28 17:08:01 -05:00
VX_gpr_req_if.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_gpr_rsp_if.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_gpu_req_if.v
SCOPE update
2020-09-05 10:52:59 -07:00
VX_ibuffer_if.v
instr_sched => ibuffer
2021-06-27 19:36:43 -07:00
VX_icache_core_req_if.v
refactoring cache_config
2021-05-27 14:41:46 -07:00
VX_icache_core_rsp_if.v
refactoring cache_config
2021-05-27 14:41:46 -07:00
VX_ifetch_req_if.v
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
VX_ifetch_rsp_if.v
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
2020-12-19 02:45:06 -08:00
VX_join_if.v
optimize warp_sched
2020-08-24 05:36:00 -07:00
VX_lsu_req_if.v
adding data fence support
2021-06-28 06:12:18 -07:00
VX_perf_cache_if.v
perf counters generic size
2021-04-25 21:15:24 -07:00
VX_perf_memsys_if.v
code refactoring: DRAM => MEM renaming
2021-04-26 00:58:48 -07:00
VX_perf_pipeline_if.v
perf counters generic size
2021-04-25 21:15:24 -07:00
VX_warp_ctl_if.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_writeback_if.v
scoreboard optimization - using writeback's end-of-packet status
2020-12-30 06:47:56 -08:00
VX_wstall_if.v
tabs cleanup
2020-11-28 17:08:01 -05:00