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refactoring cache_config

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This commit is contained in:
Blaise Tine
2021-05-27 14:41:46 -07:00
parent 321a2c5e1b
commit 5d2437d887
16 changed files with 15 additions and 15 deletions
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2
hw/rtl/cache/VX_bank.v vendored
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@@ -1,4 +1,4 @@
`include "VX_cache_config.vh"
`include "VX_cache_define.vh"
module VX_bank #(
parameter CACHE_ID = 0,

2
hw/rtl/cache/VX_cache.v vendored
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@@ -1,4 +1,4 @@
`include "VX_cache_config.vh"
`include "VX_cache_define.vh"
module VX_cache #(
parameter CACHE_ID = 0,

2
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
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@@ -1,4 +1,4 @@
`include "VX_cache_config.vh"
`include "VX_cache_define.vh"
module VX_cache_core_req_bank_sel #(
parameter CACHE_ID = 0,

2
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -1,4 +1,4 @@
`include "VX_cache_config.vh"
`include "VX_cache_define.vh"
module VX_cache_core_rsp_merge #(
parameter CACHE_ID = 0,

0
hw/rtl/cache/VX_cache_config.vh → hw/rtl/cache/VX_cache_define.vh vendored
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2
hw/rtl/cache/VX_data_access.v vendored
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@@ -1,4 +1,4 @@
`include "VX_cache_config.vh"
`include "VX_cache_define.vh"
module VX_data_access #(
parameter CACHE_ID = 0,

2
hw/rtl/cache/VX_flush_ctrl.v vendored
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@@ -1,4 +1,4 @@
`include "VX_cache_config.vh"
`include "VX_cache_define.vh"
module VX_flush_ctrl #(
// Size of cache in bytes

2
hw/rtl/cache/VX_miss_resrv.v vendored
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@@ -1,4 +1,4 @@
`include "VX_cache_config.vh"
`include "VX_cache_define.vh"
module VX_miss_resrv #(
parameter CACHE_ID = 0,

2
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -1,4 +1,4 @@
`include "VX_cache_config.vh"
`include "VX_cache_define.vh"
module VX_shared_mem #(
parameter CACHE_ID = 0,

2
hw/rtl/cache/VX_tag_access.v vendored
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@@ -1,4 +1,4 @@
`include "VX_cache_config.vh"
`include "VX_cache_define.vh"
module VX_tag_access #(
parameter CACHE_ID = 0,

2
hw/rtl/interfaces/VX_cache_mem_req_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_CACHE_MEM_REQ_IF
`define VX_CACHE_MEM_REQ_IF
`include "../cache/VX_cache_config.vh"
`include "../cache/VX_cache_define.vh"
interface VX_cache_mem_req_if #(
parameter MEM_LINE_WIDTH = 1,

2
hw/rtl/interfaces/VX_cache_mem_rsp_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_CACHE_MEM_RSP_IF
`define VX_CACHE_MEM_RSP_IF
`include "../cache/VX_cache_config.vh"
`include "../cache/VX_cache_define.vh"
interface VX_cache_mem_rsp_if #(
parameter MEM_LINE_WIDTH = 1,

2
hw/rtl/interfaces/VX_dcache_core_req_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_DCACHE_CORE_REQ_IF
`define VX_DCACHE_CORE_REQ_IF
`include "../cache/VX_cache_config.vh"
`include "../cache/VX_cache_define.vh"
interface VX_dcache_core_req_if #(
parameter NUM_REQS = 1,

2
hw/rtl/interfaces/VX_dcache_core_rsp_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_DCACHE_CORE_RSP_IF
`define VX_DCACHE_CORE_RSP_IF
`include "../cache/VX_cache_config.vh"
`include "../cache/VX_cache_define.vh"
interface VX_dcache_core_rsp_if #(
parameter NUM_REQS = 1,

2
hw/rtl/interfaces/VX_icache_core_req_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_ICACHE_CORE_REQ_IF
`define VX_ICACHE_CORE_REQ_IF
`include "../cache/VX_cache_config.vh"
`include "../cache/VX_cache_define.vh"
interface VX_icache_core_req_if #(
parameter WORD_SIZE = 1,

2
hw/rtl/interfaces/VX_icache_core_rsp_if.v
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@@ -1,7 +1,7 @@
`ifndef VX_ICACHE_CORE_RSP_IF
`define VX_ICACHE_CORE_RSP_IF
`include "../cache/VX_cache_config.vh"
`include "../cache/VX_cache_define.vh"
interface VX_icache_core_rsp_if #(
parameter WORD_SIZE = 1,