15 lines
263 B
Verilog
15 lines
263 B
Verilog
`ifndef VX_BRANCH_RSP_IF
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`define VX_BRANCH_RSP_IF
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`include "VX_define.vh"
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interface VX_branch_ctl_if ();
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wire valid;
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wire [`NW_BITS-1:0] warp_num;
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wire taken;
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wire [31:0] dest;
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endinterface
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`endif |