53 lines
3.9 KiB
Plaintext
53 lines
3.9 KiB
Plaintext
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
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C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
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S 26 40239138 1574470136 "../rtl/./VX_define_synth.v"
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S 283 40239133 1574470136 "../rtl/VX_countones.v"
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S 7240 40239137 1574470136 "../rtl/VX_define.v"
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S 8325 40239139 1574470136 "../rtl/VX_dmem_controller.v"
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S 517 40239143 1574470136 "../rtl/VX_generic_priority_encoder.v"
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S 683 40239154 1574470136 "../rtl/VX_priority_encoder_w_mask.v"
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S 8590 40239164 1574470136 "../rtl/cache/VX_Cache_Bank.v"
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S 748 40239165 1574470136 "../rtl/cache/VX_cache_bank_valid.v"
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S 7349 40239166 1574470136 "../rtl/cache/VX_cache_data.v"
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S 6476 40239167 1574470136 "../rtl/cache/VX_cache_data_per_index.v"
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S 14645 40239168 1574470136 "../rtl/cache/VX_d_cache.v"
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S 393 40239180 1574470136 "../rtl/interfaces/VX_dcache_request_inter.v"
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S 215 40239181 1574470136 "../rtl/interfaces/VX_dcache_response_inter.v"
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S 870 40239182 1574470136 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
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S 354 40239191 1574470136 "../rtl/interfaces/VX_icache_request_inter.v"
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S 212 40239192 1574470136 "../rtl/interfaces/VX_icache_response_inter.v"
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S 7240 40239137 1574470136 "../rtl/shared_memory/../VX_define.v"
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S 676 40239236 1574470136 "../rtl/shared_memory/VX_bank_valids.v"
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S 3038 40239237 1574470136 "../rtl/shared_memory/VX_priority_encoder_sm.v"
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S 4962 40239238 1574470136 "../rtl/shared_memory/VX_shared_memory.v"
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S 3207 40239239 1574470136 "../rtl/shared_memory/VX_shared_memory_block.v"
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S 4117944 1442940 1433741508 "/usr/bin/verilator_bin"
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S 3144 40239440 1574470137 "cache_simX.v"
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T 9461 40501257 1574470340 "obj_dir/Vcache_simX.cpp"
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T 5060 40501256 1574470340 "obj_dir/Vcache_simX.h"
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T 2505 40501275 1574470341 "obj_dir/Vcache_simX.mk"
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T 836 40501271 1574470341 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
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T 1627 40501270 1574470341 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
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T 721 40501273 1574470341 "obj_dir/Vcache_simX_VX_dcache_response_inter.cpp"
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T 1529 40501272 1574470341 "obj_dir/Vcache_simX_VX_dcache_response_inter.h"
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T 1690042 40501261 1574470341 "obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.cpp"
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T 145427 40501260 1574470340 "obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.h"
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T 792 40501269 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
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T 1615 40501268 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
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T 792 40501267 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
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T 1616 40501266 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
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T 716 40501263 1574470341 "obj_dir/Vcache_simX_VX_icache_request_inter.cpp"
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T 1520 40501262 1574470341 "obj_dir/Vcache_simX_VX_icache_request_inter.h"
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T 721 40501265 1574470341 "obj_dir/Vcache_simX_VX_icache_response_inter.cpp"
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T 1529 40501264 1574470341 "obj_dir/Vcache_simX_VX_icache_response_inter.h"
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T 735 40501251 1574470340 "obj_dir/Vcache_simX__Inlines.h"
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T 2656 40501253 1574470340 "obj_dir/Vcache_simX__Syms.cpp"
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T 1907 40501252 1574470340 "obj_dir/Vcache_simX__Syms.h"
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T 656053 40501255 1574470340 "obj_dir/Vcache_simX__Trace.cpp"
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T 854791 40501254 1574470340 "obj_dir/Vcache_simX__Trace__Slow.cpp"
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T 1868 40501276 1574470341 "obj_dir/Vcache_simX__ver.d"
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T 0 0 1574470341 "obj_dir/Vcache_simX__verFiles.dat"
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T 5999 40501259 1574470340 "obj_dir/Vcache_simX_cache_simX.cpp"
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T 2955 40501258 1574470340 "obj_dir/Vcache_simX_cache_simX.h"
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T 1488 40501274 1574470341 "obj_dir/Vcache_simX_classes.mk"
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