53 lines
1.4 KiB
Verilog
53 lines
1.4 KiB
Verilog
`include "VX_define.vh"
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module VX_matrix_arbiter #(
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parameter N = 0
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) (
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input wire clk,
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input wire reset,
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input wire [N-1:0] requests,
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output wire grant_valid,
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output wire [N-1:0] grant_onehot,
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output wire [`LOG2UP(N)-1:0] grant_index
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);
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reg [N-1:0] state [0:N-1];
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wire [N-1:0] dis [0:N-1];
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genvar i, j;
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for (i = 0; i < N; ++i) begin
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for (j = i + 1; j < N; ++j) begin
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always @(posedge clk) begin
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if (reset) begin
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state[i][j] <= 0;
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end else begin
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state[i][j] <= (state[i][j] || grant_onehot[j]) && ~grant_onehot[i];
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end
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end
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end
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end
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for (i = 0; i < N; ++i) begin
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for (j = 0; j < N; ++j) begin
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if (j > i) begin
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assign dis[j][i] = requests[i] & state[i][j];
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end else if (j < i) begin
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assign dis[j][i] = requests[i] & ~state[j][i];
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end else begin
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assign dis[j][i] = 0;
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end
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end
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assign grant_onehot[i] = requests[i] & ~(| dis[i]);
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end
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VX_encoder_onehot #(
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.N(N)
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) encoder (
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.onehot(grant_onehot),
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.valid(grant_valid),
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.value(grant_index)
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);
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endmodule |