502 lines
16 KiB
C++
502 lines
16 KiB
C++
#include "cache.h"
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#include "debug.h"
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#include "types.h"
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#include <util.h>
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#include <unordered_map>
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#include <vector>
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#include <list>
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#include <queue>
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using namespace vortex;
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struct params_t {
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uint32_t sets_per_bank;
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uint32_t blocks_per_set;
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uint32_t words_per_block;
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uint32_t word_select_addr_start;
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uint32_t word_select_addr_end;
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uint32_t bank_select_addr_start;
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uint32_t bank_select_addr_end;
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uint32_t set_select_addr_start;
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uint32_t set_select_addr_end;
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uint32_t tag_select_addr_start;
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uint32_t tag_select_addr_end;
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params_t(const CacheConfig& config) {
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uint32_t bank_bits = log2ceil(config.num_banks);
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uint32_t offset_bits = config.B - config.W;
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uint32_t log2_bank_size = config.C - bank_bits;
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uint32_t index_bits = log2_bank_size - (config.B << config.A);
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assert(log2_bank_size >= config.B);
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this->words_per_block = 1 << offset_bits;
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this->blocks_per_set = 1 << config.A;
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this->sets_per_bank = 1 << index_bits;
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assert(config.ports_per_bank <= this->words_per_block);
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// Word select
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this->word_select_addr_start = config.W;
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this->word_select_addr_end = (this->word_select_addr_start+offset_bits-1);
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// Bank select
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this->bank_select_addr_start = (1+this->word_select_addr_end);
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this->bank_select_addr_end = (this->bank_select_addr_start+bank_bits-1);
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// Set select
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this->set_select_addr_start = (1+this->bank_select_addr_end);
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this->set_select_addr_end = (this->set_select_addr_start+index_bits-1);
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// Tag select
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this->tag_select_addr_start = (1+this->set_select_addr_end);
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this->tag_select_addr_end = (config.addr_width-1);
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}
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uint32_t addr_bank_id(uint64_t word_addr) const {
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if (bank_select_addr_end >= bank_select_addr_start)
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return (uint32_t)bit_getw(word_addr, bank_select_addr_start, bank_select_addr_end);
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else
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return 0;
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}
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uint32_t addr_set_id(uint64_t word_addr) const {
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if (set_select_addr_end >= set_select_addr_start)
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return (uint32_t)bit_getw(word_addr, set_select_addr_start, set_select_addr_end);
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else
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return 0;
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}
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uint64_t addr_tag(uint64_t word_addr) const {
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if (tag_select_addr_end >= tag_select_addr_start)
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return bit_getw(word_addr, tag_select_addr_start, tag_select_addr_end);
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else
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return 0;
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}
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uint64_t mem_addr(uint32_t bank_id, uint32_t set_id, uint64_t tag) const {
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uint64_t addr(0);
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if (bank_select_addr_end >= bank_select_addr_start)
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addr = bit_setw(addr, bank_select_addr_start, bank_select_addr_end, bank_id);
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if (set_select_addr_end >= set_select_addr_start)
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addr = bit_setw(addr, set_select_addr_start, set_select_addr_end, set_id);
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if (tag_select_addr_end >= tag_select_addr_start)
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addr = bit_setw(addr, tag_select_addr_start, tag_select_addr_end, tag);
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return addr;
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}
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};
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struct block_t {
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bool valid;
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bool dirty;
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uint64_t tag;
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uint32_t lru_ctr;
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};
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struct set_t {
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std::vector<block_t> blocks;
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set_t(uint32_t size) : blocks(size) {}
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};
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struct bank_req_info_t {
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bool valid;
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uint32_t req_id;
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uint32_t req_tag;
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};
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struct bank_req_t {
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bool valid;
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bool write;
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bool mshr_replay;
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uint64_t tag;
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uint32_t set_id;
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std::vector<bank_req_info_t> infos;
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bank_req_t(uint32_t size)
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: valid(false)
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, write(false)
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, mshr_replay(false)
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, tag(0)
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, set_id(0)
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, infos(size)
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{}
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};
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struct mshr_entry_t : public bank_req_t {
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uint32_t block_id;
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mshr_entry_t(uint32_t size = 0)
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: bank_req_t(size)
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, block_id(0)
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{}
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};
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class MSHR {
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private:
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std::vector<mshr_entry_t> entries_;
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uint32_t capacity_;
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public:
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MSHR(uint32_t size)
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: entries_(size)
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, capacity_(0)
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{}
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bool empty() const {
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return (0 == capacity_);
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}
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bool full() const {
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return (capacity_ == entries_.size());
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}
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int lookup(const bank_req_t& bank_req) {
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for (uint32_t i = 0, n = entries_.size(); i < n; ++i) {
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auto& entry = entries_.at(i);
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if (entry.valid
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&& entry.set_id == bank_req.set_id
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&& entry.tag == bank_req.tag) {
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return i;
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}
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}
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return -1;
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}
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int allocate(const bank_req_t& bank_req, uint32_t block_id) {
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for (uint32_t i = 0, n = entries_.size(); i < n; ++i) {
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auto& entry = entries_.at(i);
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if (!entry.valid) {
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*(bank_req_t*)&entry = bank_req;
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entry.valid = true;
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entry.mshr_replay = false;
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entry.block_id = block_id;
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++capacity_;
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return i;
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}
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}
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return -1;
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}
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mshr_entry_t& replay(uint32_t id) {
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auto& root_entry = entries_.at(id);
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assert(root_entry.valid);
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// make all related mshr entries for replay
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for (auto& entry : entries_) {
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if (entry.valid
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&& entry.set_id == root_entry.set_id
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&& entry.tag == root_entry.tag) {
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entry.mshr_replay = true;
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}
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}
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return root_entry;
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}
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bool try_pop(bank_req_t* out) {
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for (auto& entry : entries_) {
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if (entry.valid && entry.mshr_replay) {
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*out = entry;
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entry.valid = false;
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--capacity_;
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return true;
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}
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}
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return false;
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}
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};
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struct bank_t {
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std::vector<set_t> sets;
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MSHR mshr;
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std::queue<bank_req_t> stall_buffer;
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bank_req_t active_req;
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bank_t(const CacheConfig& config,
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const params_t& params)
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: sets(params.sets_per_bank, params.blocks_per_set)
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, mshr(config.mshr_size)
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, active_req(config.ports_per_bank)
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{}
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};
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///////////////////////////////////////////////////////////////////////////////
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class Cache::Impl {
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private:
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Cache* const simobject_;
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CacheConfig config_;
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params_t params_;
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std::vector<bank_t> banks_;
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std::vector<std::queue<uint32_t>> core_rsps_;
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Switch<MemReq, MemRsp>::Ptr mem_switch_;
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std::vector<MasterPort<MemReq>> mem_req_ports_;
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std::vector<SlavePort<MemRsp>> mem_rsp_ports_;
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public:
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Impl(Cache* simobject, const CacheConfig& config)
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: simobject_(simobject)
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, config_(config)
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, params_(config)
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, banks_(config.num_banks, {config, params_})
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, core_rsps_(config.num_inputs)
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, mem_req_ports_(config.num_banks, simobject)
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, mem_rsp_ports_(config.num_banks, simobject)
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{
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if (config.num_banks > 1) {
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mem_switch_ = Switch<MemReq, MemRsp>::Create("mem_arb", ArbiterType::RoundRobin, config.num_banks);
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for (uint32_t i = 0, n = config.num_banks; i < n; ++i) {
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mem_req_ports_.at(i).bind(&mem_switch_->ReqIn.at(i));
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mem_switch_->RspOut.at(i).bind(&mem_rsp_ports_.at(i));
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}
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mem_switch_->ReqOut.bind(&simobject->MemReqPort);
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simobject->MemRspPort.bind(&mem_switch_->RspIn);
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} else {
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mem_req_ports_.at(0).bind(&simobject->MemReqPort);
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simobject->MemRspPort.bind(&mem_rsp_ports_.at(0));
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}
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}
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void step(uint64_t /*cycle*/) {
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// process core response
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for (uint32_t req_id = 0, n = config_.num_inputs; req_id < n; ++req_id) {
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auto& core_rsp = core_rsps_.at(req_id);
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if (!core_rsp.empty()) {
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simobject_->CoreRspPorts.at(req_id).send(MemRsp{core_rsp.front()}, config_.latency);
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core_rsp.pop();
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}
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}
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for (auto& bank : banks_) {
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auto& active_req = bank.active_req;
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// try chedule mshr replay
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if (!active_req.valid) {
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bank.mshr.try_pop(&active_req);
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}
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// try schedule stall queue if MSHR has space
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if (!active_req.valid
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&& !bank.stall_buffer.empty()
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&& !bank.mshr.full()) {
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active_req = bank.stall_buffer.front();
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bank.stall_buffer.pop();
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}
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}
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// handle memory fills
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for (uint32_t i = 0, n = config_.num_banks; i < n; ++i) {
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MemRsp mem_rsp;
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if (mem_rsp_ports_.at(i).read(&mem_rsp)) {
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this->processMemoryFill(i, mem_rsp.tag);
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}
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}
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// handle incoming core requests
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for (uint32_t i = 0, n = config_.num_inputs; i < n; ++i) {
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MemReq core_req;
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if (!simobject_->CoreReqPorts.at(i).read(&core_req))
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continue;
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auto bank_id = params_.addr_bank_id(core_req.addr);
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auto set_id = params_.addr_set_id(core_req.addr);
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auto tag = params_.addr_tag(core_req.addr);
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auto port_id = i % config_.ports_per_bank;
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// create abnk request
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bank_req_t bank_req(config_.ports_per_bank);
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bank_req.valid = true;
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bank_req.write = core_req.write;
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bank_req.mshr_replay = false;
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bank_req.tag = tag;
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bank_req.set_id = set_id;
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bank_req.infos.at(port_id) = {true, i, core_req.tag};
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auto& bank = banks_.at(bank_id);
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// check MSHR capacity
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if (bank.mshr.full()) {
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// add to stall buffer
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bank.stall_buffer.emplace(bank_req);
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continue;
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}
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auto& active_req = bank.active_req;
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// check pending MSHR request
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if (active_req.valid
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&& active_req.mshr_replay) {
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// add to stall buffer
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bank.stall_buffer.emplace(bank_req);
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continue;
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}
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// check bank conflicts
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if (active_req.valid) {
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// check port conflict
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if (active_req.write != core_req.write
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|| active_req.set_id != set_id
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|| active_req.tag != tag
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|| active_req.infos[port_id].valid) {
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// add to stall buffer
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bank.stall_buffer.emplace(bank_req);
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continue;
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}
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// update pending request infos
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active_req.infos[port_id] = bank_req.infos[port_id];
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} else {
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// schedule new request
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active_req = bank_req;
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}
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}
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// process active request
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for (uint32_t bank_id = 0, n = config_.num_banks; bank_id < n; ++bank_id) {
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this->processBankRequest(bank_id);
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}
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}
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void processMemoryFill(uint32_t bank_id, uint32_t mshr_id) {
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// update block
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auto& bank = banks_.at(bank_id);
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auto& root_entry = bank.mshr.replay(mshr_id);
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auto& set = bank.sets.at(root_entry.set_id);
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auto& block = set.blocks.at(root_entry.block_id);
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block.valid = true;
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block.tag = root_entry.tag;
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}
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void processBankRequest(uint32_t bank_id) {
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auto& bank = banks_.at(bank_id);
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auto& active_req = bank.active_req;
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if (!active_req.valid)
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return;
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active_req.valid = false;
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auto& set = bank.sets.at(active_req.set_id);
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if (active_req.mshr_replay) {
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// send core response
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for (auto& info : active_req.infos) {
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core_rsps_.at(info.req_id).emplace(info.req_tag);
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}
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} else {
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bool hit = false;
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bool found_free_block = false;
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int hit_block_id = 0;
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int repl_block_id = 0;
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uint32_t max_cnt = 0;
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for (int i = 0, n = set.blocks.size(); i < n; ++i) {
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auto& block = set.blocks.at(i);
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if (block.valid) {
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if (block.tag == active_req.tag) {
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block.lru_ctr = 0;
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hit_block_id = i;
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hit = true;
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} else {
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++block.lru_ctr;
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}
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if (max_cnt < block.lru_ctr) {
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max_cnt = block.lru_ctr;
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repl_block_id = i;
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}
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} else {
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found_free_block = true;
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repl_block_id = i;
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}
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}
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if (hit) {
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//
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// MISS handling
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//
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if (active_req.write) {
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// handle write hit
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auto& hit_block = set.blocks.at(hit_block_id);
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if (config_.write_through) {
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// forward write request to memory
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MemReq mem_req;
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mem_req.addr = params_.mem_addr(bank_id, active_req.set_id, hit_block.tag);
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mem_req.write = true;
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mem_req.tag = 0;
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mem_req_ports_.at(bank_id).send(mem_req, 1);
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} else {
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// mark block as dirty
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hit_block.dirty = true;
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}
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}
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// send core response
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for (auto& info : active_req.infos) {
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core_rsps_.at(info.req_id).emplace(info.req_tag);
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}
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} else {
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//
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// MISS handling
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//
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if (!found_free_block && !config_.write_through) {
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// write back dirty block
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auto& repl_block = set.blocks.at(repl_block_id);
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if (repl_block.dirty) {
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MemReq mem_req;
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mem_req.addr = params_.mem_addr(bank_id, active_req.set_id, repl_block.tag);
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mem_req.write = true;
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mem_req.tag = 0;
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mem_req_ports_.at(bank_id).send(mem_req, 1);
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}
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}
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if (active_req.write && config_.write_through) {
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// forward write request to memory
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{
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MemReq mem_req;
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mem_req.addr = params_.mem_addr(bank_id, active_req.set_id, active_req.tag);
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mem_req.write = true;
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mem_req.tag = 0;
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mem_req_ports_.at(bank_id).send(mem_req, 1);
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}
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// send core response
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for (auto& info : active_req.infos) {
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core_rsps_.at(info.req_id).emplace(info.req_tag);
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}
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} else {
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// lookup
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int pending = bank.mshr.lookup(active_req);
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// allocate MSHR
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int mshr_id = bank.mshr.allocate(active_req, repl_block_id);
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// send fill request
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if (pending == -1) {
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MemReq mem_req;
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mem_req.addr = params_.mem_addr(bank_id, active_req.set_id, active_req.tag);
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mem_req.write = active_req.write;
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mem_req.tag = mshr_id;
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mem_req_ports_.at(bank_id).send(mem_req, 1);
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}
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}
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}
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}
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}
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};
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///////////////////////////////////////////////////////////////////////////////
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Cache::Cache(const SimContext& ctx, const char* name, const CacheConfig& config)
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: SimObject<Cache>(ctx, name)
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, CoreReqPorts(config.num_inputs, this)
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, CoreRspPorts(config.num_inputs, this)
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, MemReqPort(this)
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, MemRspPort(this)
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, impl_(new Impl(this, config))
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{}
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Cache::~Cache() {
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delete impl_;
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}
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void Cache::step(uint64_t cycle) {
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impl_->step(cycle);
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} |