46 lines
3.7 KiB
C++
46 lines
3.7 KiB
C++
// Verilated -*- C++ -*-
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// DESCRIPTION: Verilator output: Symbol table implementation internals
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#include "Vcache_simX__Syms.h"
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#include "Vcache_simX.h"
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#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
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#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
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#include "Vcache_simX_VX_dcache_request_inter.h"
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#include "Vcache_simX_VX_Cache_Bank__pi8.h"
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// FUNCTIONS
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Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
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// Setup locals
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: __Vm_namep(namep)
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, __Vm_activity(false)
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, __Vm_didInit(false)
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// Setup submodule names
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, TOP__cache_simX__DOT__VX_dcache_req (Verilated::catName(topp->name(),"cache_simX.VX_dcache_req"))
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, TOP__cache_simX__DOT__VX_dram_req_rsp (Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp"))
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, TOP__cache_simX__DOT__VX_dram_req_rsp_icache (Verilated::catName(topp->name(),"cache_simX.VX_dram_req_rsp_icache"))
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, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[0].bank_structure"))
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, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[1].bank_structure"))
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, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[2].bank_structure"))
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, TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure (Verilated::catName(topp->name(),"cache_simX.dmem_controller.dcache.genblk3[3].bank_structure"))
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{
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// Pointer to top level
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TOPp = topp;
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// Setup each module's pointers to their submodules
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TOPp->__PVT__cache_simX__DOT__VX_dcache_req = &TOP__cache_simX__DOT__VX_dcache_req;
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TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp = &TOP__cache_simX__DOT__VX_dram_req_rsp;
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TOPp->__PVT__cache_simX__DOT__VX_dram_req_rsp_icache = &TOP__cache_simX__DOT__VX_dram_req_rsp_icache;
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TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure;
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TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure;
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TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure;
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TOPp->__PVT__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure = &TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure;
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// Setup each module's pointer back to symbol table (for public functions)
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TOPp->__Vconfigure(this, true);
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TOP__cache_simX__DOT__VX_dcache_req.__Vconfigure(this, true);
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TOP__cache_simX__DOT__VX_dram_req_rsp.__Vconfigure(this, true);
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TOP__cache_simX__DOT__VX_dram_req_rsp_icache.__Vconfigure(this, true);
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TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__0__KET____DOT__bank_structure.__Vconfigure(this, true);
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TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__1__KET____DOT__bank_structure.__Vconfigure(this, false);
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TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__2__KET____DOT__bank_structure.__Vconfigure(this, false);
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TOP__cache_simX__DOT__dmem_controller__DOT__dcache__DOT__genblk3__BRA__3__KET____DOT__bank_structure.__Vconfigure(this, false);
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}
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