wgulian3 e9cdc6e5af SystemVerilog tweaks to appease Quartus and make Quartus synthesis work

2020-01-24 06:10:24 -05:00

..

cache_set.v

Modelsim basic sim

2019-10-26 00:34:57 -04:00

d_cache_test_bench_debug.h

Finished Cache Integration

2019-10-22 06:02:08 -04:00

d_cache_test_bench.cpp

Finished Cache Integration

2019-10-22 06:02:08 -04:00

d_cache_test_bench.h

Finished Cache Integration

2019-10-22 06:02:08 -04:00

Makefile

Finished Cache Integration

2019-10-22 06:02:08 -04:00

Notes

Finished Cache Integration

2019-10-22 06:02:08 -04:00

VX_cache_bank_valid.v

Started simX

2019-11-10 01:21:09 -05:00

VX_Cache_Bank.v

SystemVerilog tweaks to appease Quartus and make Quartus synthesis work

2020-01-24 06:10:24 -05:00

VX_cache_data_per_index.v

SystemVerilog tweaks to appease Quartus and make Quartus synthesis work

2020-01-24 06:10:24 -05:00

VX_cache_data.v

Switched to g++

2019-11-16 12:23:59 -05:00

VX_d_cache_encapsulate.v

SystemVerilog tweaks to appease Quartus and make Quartus synthesis work

2020-01-24 06:10:24 -05:00

VX_d_cache_tb.v

Finished Cache Integration

2019-10-22 06:02:08 -04:00

VX_d_cache.v

SystemVerilog tweaks to appease Quartus and make Quartus synthesis work

2020-01-24 06:10:24 -05:00

VX_generic_pe.v

Finished Cache Integration

2019-10-22 06:02:08 -04:00