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  • 22f02820cf GPR back-end with mem felsabbagh3 2019-10-14 19:10:47 -04:00
  • ee83e6d8c8 Moved GPR to back-end felsabbagh3 2019-10-14 19:08:32 -04:00
  • 5680b997b5 Generate LIB files for rf2_32x128_wm1 Lingjun Zhu 2019-10-14 17:08:18 -04:00
  • f28cd286e6 Implemented the GPR model with the CLN28HPC memory block Lingjun Zhu 2019-10-13 20:27:28 -04:00
  • d5dad1c442 Updated the two-port GPR model Lingjun Zhu 2019-10-13 19:52:14 -04:00
  • 8af8c67299 Implemented the two-port GPR model Lingjun Zhu 2019-10-13 19:44:50 -04:00
  • b9d2e09d78 Move the memory models from Cache_Progress to Master branch Lingjun Zhu 2019-10-13 13:13:42 -04:00
  • e67310acfb New Warp Scheduler + VCD Enable felsabbagh3 2019-09-15 00:12:41 -04:00
  • fb3bc60189 Finalized GPR with 3-Port Structure felsabbagh3 2019-09-11 14:53:32 -04:00
  • 1b25b10644 Full Evaluation Attempt 1 felsabbagh3 2019-09-11 01:39:00 -04:00
  • 3c3a443bd5 New RF with Evaluation felsabbagh3 2019-09-11 01:04:23 -04:00
  • 8d143d7739 Quartus + GPR evaluation felsabbagh3 2019-09-10 20:23:01 -04:00
  • 4e8da1811a New GPR structure - Clone or WSPAWN felsabbagh3 2019-09-09 22:17:20 -04:00
  • 1882147370 GPR Wrapper Interface Done felsabbagh3 2019-09-09 14:04:07 -04:00
  • bce9bc443c GPR Wrapper in Decode felsabbagh3 2019-09-09 01:03:13 -04:00
  • ecf81336db Finished FE and BE high-level felsabbagh3 2019-09-08 19:28:53 -04:00
  • 981bf0afe5 FE Done felsabbagh3 2019-09-08 18:36:47 -04:00
  • ad45758a35 Before Fetch->FE felsabbagh3 2019-09-08 18:09:11 -04:00
  • c310e7381f Icache interface felsabbagh3 2019-09-08 17:36:09 -04:00
  • 5e6804703f Decode in FE felsabbagh3 2019-09-08 17:24:51 -04:00
  • ac9b06bf7d Before FE BE abstraction felsabbagh3 2019-09-08 16:21:37 -04:00
  • fe09aafbb4 Interface Checkpoint 2 - Remove Lints felsabbagh3 2019-09-05 19:32:37 -04:00
  • 2d0e41db63 checkpoint: Added icache struct felsabbagh3 2019-09-03 16:19:06 -04:00
  • cde45648ea Added Bug coments felsabbagh3 2019-06-12 08:27:48 -07:00
  • 3e93301846 Added Bug coments felsabbagh3 2019-06-12 08:26:04 -07:00
  • 32d1bfb140 Barrier bug comment felsabbagh3 2019-06-12 08:22:03 -07:00
  • db0860a7fb Recompiled kernel felsabbagh3 2019-06-12 08:09:31 -07:00
  • b76d819d82 Merge branch 'master' of https://github.gatech.edu/casl/Vortex felsabbagh3 2019-06-12 08:03:59 -07:00
  • b3256a7b7f Fix barrier bug felsabbagh3 2019-06-12 08:03:30 -07:00
  • 6b3b124a30 fix typo of std=c++11 Hyesoon Kim 2019-06-12 07:32:20 -04:00
  • 9cd8ee8579 Added std=c++11 felsabbagh3 2019-06-11 23:21:48 -07:00
  • 1105261bbb Updated Quartus paths felsabbagh3 2019-06-11 21:16:50 -07:00
  • b216da5a6a ram stdint + Quartus Files felsabbagh3 2019-06-11 21:13:30 -07:00
  • d7afef04a9 Sim Work miss felsabbagh3 2019-05-18 23:42:55 +04:00
  • 8995267cd3 Added barriers felsabbagh3 2019-05-17 08:34:00 +04:00
  • 48468ed26a Proper SIMT with fine-grain scheduler implemented felsabbagh3 2019-05-10 00:49:54 -07:00
  • 96dac5e1ce Warp + Context Aware Design - Global Stalling felsabbagh3 2019-05-08 16:32:49 -07:00
  • a6c13bc38c Inefficient context aware desgin felsabbagh3 2019-05-08 15:55:06 -07:00
  • 79356c7ab1 Changed hierarchy + Identified private + public modules felsabbagh3 2019-05-07 23:45:05 -07:00
  • 191ed73415 Less expensive but slower fetch logic felsabbagh3 2019-05-05 22:55:47 -04:00
  • f21eaec79f Provisioned SM felsabbagh3 2019-04-05 19:25:54 -04:00
  • 166b9ae48d Before Scratchpad felsabbagh3 2019-04-05 17:56:05 -04:00
  • 719ed25213 Cleanup felsabbagh3 2019-03-31 16:30:37 -04:00
  • 26378d61d8 updated TODO felsabbagh3 2019-03-31 05:22:42 -04:00
  • 8c2ae97510 1 WARP 8 THREADS TESTED + FULLY WORKING felsabbagh3 2019-03-31 05:21:00 -04:00
  • c83ef94d02 1 WARP 2 THREADS WORKING felsabbagh3 2019-03-31 05:02:55 -04:00
  • 4aac33b298 Using verilog For-loops + Passing all tests felsabbagh3 2019-03-30 22:55:13 -04:00
  • 52a839f84d Using verilog For-loops + Passing all tests felsabbagh3 2019-03-30 22:14:44 -04:00
  • a3a3b21de7 Using verilog For-loops + Passing all tests felsabbagh3 2019-03-30 22:09:03 -04:00
  • 99a0792a0c Passing all tests with 2 threads felsabbagh3 2019-03-30 03:54:20 -04:00
  • d02c3d25b7 sync felsabbagh3 2019-03-27 13:52:13 -04:00
  • 68f3ba84e5 Added HW threads - Infinite loop + fixed valid felsabbagh3 2019-03-27 03:53:59 -04:00
  • 9b42e79dcf Added HW threads - Infinite loop felsabbagh3 2019-03-27 03:44:14 -04:00
  • cc0fb0eece better use of valid signal felsabbagh3 2019-03-27 00:07:59 -04:00
  • 7a528c5ef2 Packing data wires + ALU module felsabbagh3 2019-03-26 19:17:11 -04:00
  • 6901208a54 Added a README felsabbagh3 2019-03-22 04:29:24 -04:00
  • d42e7845a9 Added a README felsabbagh3 2019-03-22 04:27:42 -04:00
  • 781c11c93f Updated TODO felsabbagh3 2019-03-22 04:21:21 -04:00
  • 6c64fa35f8 Restructure felsabbagh3 2019-03-22 04:14:52 -04:00
  • 097e0217de Added support for MUL/DIV (Passes all tests) felsabbagh3 2019-03-22 03:54:59 -04:00
  • 01d142c6e6 rtl passing all tests felsabbagh3 2019-03-22 02:44:53 -04:00
  • 656475b3b3 Passing Most tests felsabbagh3 2019-03-21 23:47:48 -04:00
  • d08d389177 Started on rtl (Finished till decode) felsabbagh3 2019-03-21 02:23:10 -04:00
  • 1892feefbf Improved Efficiency + Added Matrix Scalar functions felsabbagh3 2019-03-19 16:37:49 -04:00
  • cae4247343 Automatic Available Warp/Thread Detection felsabbagh3 2019-03-19 14:19:00 -04:00
  • f61a013c8e updated TODO felsabbagh3 2019-03-19 01:53:55 -04:00
  • cfbf69812c 1 warp stable independance felsabbagh3 2019-03-19 01:47:23 -04:00
  • 936b98bfb5 fixed barrier bug felsabbagh3 2019-03-19 00:56:36 -04:00
  • ee0d8a0f55 Finished mult, add, and sub felsabbagh3 2019-03-19 00:43:03 -04:00
  • 4266c8d86c Changed name to vortex for now + Fixed library structure felsabbagh3 2019-03-18 21:10:16 -04:00
  • 1ebd7a6969 changed args structure felsabbagh3 2019-03-18 18:38:02 -04:00
  • 2944fe4a1b TODO: finish mult algo + make a proper OS felsabbagh3 2019-03-17 00:12:25 -04:00
  • c8af6f60ff Added support for M extension felsabbagh3 2019-03-16 23:50:01 -04:00
  • e5f1ed1af4 code cleanup felsabbagh3 2019-03-16 19:38:47 -04:00
  • 7fe17b2055 exploring compressed instructions Demo 2019-03-10 03:58:56 -04:00
  • 0215b17f01 added TODO Demo 2019-03-10 03:47:51 -04:00
  • f82a938267 Added warp independance Demo 2019-03-10 03:43:25 -04:00
  • 56706e1f38 finally added a makefile Demo 2019-03-09 13:57:06 -05:00
  • af4303a4ca Warp Scheduling + Control Divergence working and stable felsabbagh3 2019-02-22 07:00:35 -05:00
  • 087a39ccf4 Working + Stable - Mutex felsabbagh3 2019-02-22 04:01:07 -05:00
  • 96a8615a5f fixed some bugs felsabbagh3 2019-02-17 07:19:20 -05:00
  • 3958beef09 Stack smashing when scheduling third warp. felsabbagh3 2019-02-15 01:45:54 -05:00
  • 337a8669fe before queue integration felsabbagh3 2019-02-14 22:46:39 -05:00
  • 6935d52c39 MWMT tested + minor opt felsabbagh3 2019-02-14 13:41:59 -05:00
  • 6c493cc4de Completed support for WSPAWN, CLONE, and JALRS felsabbagh3 2019-02-14 03:32:58 -05:00
  • 39003073f9 implementing gpu library felsabbagh3 2019-02-14 01:54:16 -05:00
  • c3c3cb0b45 adding gpgu library Fares 2019-02-13 18:26:38 -05:00
  • 3ac246ae6a PASSING ALL TEST CASES felsabbagh3 2019-02-11 01:02:09 -05:00
  • 2c1f61196a Passes all tests - SRAI felsabbagh3 2019-02-11 00:41:07 -05:00
  • d9138a1493 mem loads and stores error cuz two seperate mem modules felsabbagh3 2019-02-10 05:54:02 -05:00
  • 3c74a13009 Passes all tests except MEM and lui? felsabbagh3 2019-02-10 05:46:18 -05:00
  • 0c3a73a896 lots of errors felsabbagh3 2019-02-09 20:17:17 -05:00
  • 8128d2e250 Changed ArchDef felsabbagh3 2019-02-09 15:57:16 -05:00
  • 6526e0ac1a test new branch felsabbagh3 2019-02-09 13:56:59 -05:00
  • c103a42fdb Added matadd.s and 2warp_matadd.s felsabbagh3 2019-02-09 13:51:24 -05:00
  • 91bfd7fa0f ignore more test output chris porter 2017-09-19 16:49:35 -04:00
  • 96621adce4 ignore dot bin files chris porter 2017-09-12 17:50:28 -04:00
  • f761c82ceb add a gitignore chris porter 2017-09-12 17:48:56 -04:00
  • 42eb8b2529 Add license. chad 2016-08-17 21:29:12 -04:00
  • accb108b9e Tidy up list of instructions in header. chad 2016-08-17 21:26:50 -04:00