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625 Commits 9 Branches 0 Tags
ec1aad1591c49b611915ae1bb68afcf6156c7dff
Commit Graph
228 Commits
Author SHA1 Message Date
felsabbagh3 b216da5a6a ram stdint + Quartus Files 2019-06-11 21:13:30 -07:00
felsabbagh3 d7afef04a9 Sim Work miss 2019-05-18 23:42:55 +04:00
felsabbagh3 8995267cd3 Added barriers 2019-05-17 08:34:00 +04:00
felsabbagh3 48468ed26a Proper SIMT with fine-grain scheduler implemented 2019-05-10 00:49:54 -07:00
felsabbagh3 96dac5e1ce Warp + Context Aware Design - Global Stalling 2019-05-08 16:32:49 -07:00
felsabbagh3 a6c13bc38c Inefficient context aware desgin 2019-05-08 15:55:06 -07:00
felsabbagh3 79356c7ab1 Changed hierarchy + Identified private + public modules 2019-05-07 23:45:05 -07:00
felsabbagh3 191ed73415 Less expensive but slower fetch logic 2019-05-05 22:55:47 -04:00
felsabbagh3 f21eaec79f Provisioned SM 2019-04-05 19:25:54 -04:00
felsabbagh3 166b9ae48d Before Scratchpad 2019-04-05 17:56:05 -04:00
felsabbagh3 719ed25213 Cleanup 2019-03-31 16:30:37 -04:00
felsabbagh3 8c2ae97510 1 WARP 8 THREADS TESTED + FULLY WORKING 2019-03-31 05:21:00 -04:00
felsabbagh3 c83ef94d02 1 WARP 2 THREADS WORKING 2019-03-31 05:02:55 -04:00
felsabbagh3 4aac33b298 Using verilog For-loops + Passing all tests 2019-03-30 22:55:13 -04:00
felsabbagh3 52a839f84d Using verilog For-loops + Passing all tests 2019-03-30 22:14:44 -04:00
felsabbagh3 a3a3b21de7 Using verilog For-loops + Passing all tests 2019-03-30 22:09:03 -04:00
felsabbagh3 99a0792a0c Passing all tests with 2 threads 2019-03-30 03:54:20 -04:00
felsabbagh3 d02c3d25b7 sync 2019-03-27 13:52:13 -04:00
felsabbagh3 68f3ba84e5 Added HW threads - Infinite loop + fixed valid 2019-03-27 03:53:59 -04:00
felsabbagh3 9b42e79dcf Added HW threads - Infinite loop 2019-03-27 03:44:14 -04:00
felsabbagh3 cc0fb0eece better use of valid signal 2019-03-27 00:07:59 -04:00
felsabbagh3 7a528c5ef2 Packing data wires + ALU module 2019-03-26 19:17:11 -04:00
felsabbagh3 781c11c93f Updated TODO 2019-03-22 04:21:21 -04:00
felsabbagh3 6c64fa35f8 Restructure 2019-03-22 04:14:52 -04:00
felsabbagh3 097e0217de Added support for MUL/DIV (Passes all tests) 2019-03-22 03:54:59 -04:00
felsabbagh3 01d142c6e6 rtl passing all tests 2019-03-22 02:44:53 -04:00
felsabbagh3 656475b3b3 Passing Most tests 2019-03-21 23:47:48 -04:00
felsabbagh3 d08d389177 Started on rtl (Finished till decode) 2019-03-21 02:23:10 -04:00