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d7afef04a91ca7cc4885617cc3bfed89e2500bda
kernels/rtl
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felsabbagh3 d7afef04a9 Sim Work miss
2019-05-18 23:42:55 +04:00
..
Makefile
1 WARP 2 THREADS WORKING
2019-03-31 05:02:55 -04:00
ram.h
Passing Most tests
2019-03-21 23:47:48 -04:00
results.txt
Sim Work miss
2019-05-18 23:42:55 +04:00
test_bench.cpp
1 WARP 2 THREADS WORKING
2019-03-31 05:02:55 -04:00
test_bench.h
Sim Work miss
2019-05-18 23:42:55 +04:00
Vortex.v
Sim Work miss
2019-05-18 23:42:55 +04:00
VX_alu.v
Cleanup
2019-03-31 16:30:37 -04:00
VX_context_slave.v
Sim Work miss
2019-05-18 23:42:55 +04:00
VX_context.v
Sim Work miss
2019-05-18 23:42:55 +04:00
VX_csr_handler.v
Passing Most tests
2019-03-21 23:47:48 -04:00
VX_d_e_reg.v
Inefficient context aware desgin
2019-05-08 15:55:06 -07:00
VX_decode.v
Sim Work miss
2019-05-18 23:42:55 +04:00
VX_define.h
Sim Work miss
2019-05-18 23:42:55 +04:00
VX_define.v
Sim Work miss
2019-05-18 23:42:55 +04:00
VX_e_m_reg.v
Inefficient context aware desgin
2019-05-08 15:55:06 -07:00
VX_execute.v
Proper SIMT with fine-grain scheduler implemented
2019-05-10 00:49:54 -07:00
VX_f_d_reg.v
Inefficient context aware desgin
2019-05-08 15:55:06 -07:00
VX_fetch.v
Sim Work miss
2019-05-18 23:42:55 +04:00
VX_forwarding.v
Inefficient context aware desgin
2019-05-08 15:55:06 -07:00
VX_m_w_reg.v
Inefficient context aware desgin
2019-05-08 15:55:06 -07:00
VX_memory.v
Proper SIMT with fine-grain scheduler implemented
2019-05-10 00:49:54 -07:00
VX_register_file_master_slave.v
Proper SIMT with fine-grain scheduler implemented
2019-05-10 00:49:54 -07:00
VX_register_file_slave.v
Proper SIMT with fine-grain scheduler implemented
2019-05-10 00:49:54 -07:00
VX_register_file.v
Proper SIMT with fine-grain scheduler implemented
2019-05-10 00:49:54 -07:00
VX_shared_memory.v
Provisioned SM
2019-04-05 19:25:54 -04:00
VX_warp.v
Sim Work miss
2019-05-18 23:42:55 +04:00
VX_writeback.v
Inefficient context aware desgin
2019-05-08 15:55:06 -07:00