felsabbagh3
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469334f23e
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MULTICORE WITH L2 WORKING
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2020-03-09 01:17:11 -07:00 |
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felsabbagh3
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f315a8a44d
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Icache working
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2020-03-08 13:59:35 -07:00 |
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felsabbagh3
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4ed62f1aad
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Fixed all Cache Warnings
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2020-03-07 14:34:05 -08:00 |
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Blaise Tine
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369c2c625c
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synthesis fixes
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2020-03-05 06:58:51 -05:00 |
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felsabbagh3
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01ae6ffafe
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Added Core Interface
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2020-03-03 22:14:56 -08:00 |
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wgulian3
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e9cdc6e5af
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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
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2020-01-24 06:10:24 -05:00 |
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Lyons, Ethan Tyler
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509850192c
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Warps/Threads Parameterization
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2019-11-21 01:14:50 -05:00 |
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felsabbagh3
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70651f0340
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Added a pipeline stage + fixed SM param errors
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2019-11-13 12:25:28 -05:00 |
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felsabbagh3
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58a9140f08
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Before evict_wb_old removal
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2019-11-07 13:27:38 -05:00 |
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felsabbagh3
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a28a1c45c1
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wsapwn tested - NOTE in vx_main.c
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2019-11-03 20:56:07 -05:00 |
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felsabbagh3
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01efe02e8b
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CACHE WORKING just needs lb/sb
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2019-10-25 03:03:09 -04:00 |
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felsabbagh3
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1e648c5819
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FIxed first circular issue
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2019-10-24 10:38:04 -04:00 |
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felsabbagh3
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de8de00f6e
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Finished cache not tested
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2019-10-23 19:07:26 -04:00 |
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felsabbagh3
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b7af8c3f34
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Integrated Shared Memory
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2019-10-22 05:03:47 -04:00 |
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felsabbagh3
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505bbc20c8
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Removed FWD
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2019-10-18 02:01:39 -04:00 |
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felsabbagh3
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6779d0fade
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Instruction Multiplex LSU/EXU 1 cycle DONE
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2019-10-17 22:29:21 -04:00 |
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