wgulian3
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61803741f8
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Merge branch 'master' into fpga_synthesis
# Conflicts:
# rtl/VX_back_end.v
# rtl/VX_gpr_stage.v
# rtl/VX_writeback.v
# rtl/simulate/test_bench.cpp
# rtl/simulate/test_bench.h
# runtime/mains/dev/Makefile
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2020-02-18 03:34:38 -05:00 |
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felsabbagh3
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be66e51613
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Added CSRs, some Load unit tests are failing
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2020-02-17 22:22:27 -08:00 |
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wgulian3
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e9cdc6e5af
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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
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2020-01-24 06:10:24 -05:00 |
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felsabbagh3
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58a9140f08
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Before evict_wb_old removal
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2019-11-07 13:27:38 -05:00 |
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felsabbagh3
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1181af1df2
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Modelsim basic sim
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2019-10-26 00:34:57 -04:00 |
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felsabbagh3
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84f5ccb484
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Added CSR TID/WID reads
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2019-10-21 02:10:05 -04:00 |
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felsabbagh3
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f7d826593f
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TMC working and tested
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2019-10-18 16:09:06 -04:00 |
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felsabbagh3
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f7b55427b4
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Added ISA2 infrastructure with bugs
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2019-10-18 05:21:32 -04:00 |
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felsabbagh3
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6779d0fade
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Instruction Multiplex LSU/EXU 1 cycle DONE
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2019-10-17 22:29:21 -04:00 |
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