Lingjun Zhu
|
8cddba46ee
|
Added rf2_32x19_wm0 again
|
2019-11-11 14:28:45 -05:00 |
|
felsabbagh3
|
3b49b82c46
|
GPR ASIC Working
|
2019-10-29 23:20:16 -04:00 |
|
felsabbagh3
|
3caae2b88e
|
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
|
2019-10-29 14:28:41 -04:00 |
|
felsabbagh3
|
4aa04e76e6
|
Simulate debug
|
2019-10-29 14:28:20 -04:00 |
|
Lingjun Zhu
|
50d567d70c
|
Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
|
2019-10-28 14:49:55 -04:00 |
|
felsabbagh3
|
b7af8c3f34
|
Integrated Shared Memory
|
2019-10-22 05:03:47 -04:00 |
|
Lingjun Zhu
|
405926f66f
|
Generated memory blocks for data cache (data), data cache (tag), shared memory
|
2019-10-20 14:52:28 -04:00 |
|
Lingjun Zhu
|
93531715bb
|
Created a testbench and simulated the read/write of the register file
|
2019-10-18 22:55:34 -04:00 |
|
Lingjun Zhu
|
84d321a517
|
Create the memory blocks with CLN28HPM
|
2019-10-17 15:38:48 -04:00 |
|
felsabbagh3
|
9a9afbbb6b
|
Updated makefile
|
2019-10-16 19:56:11 -04:00 |
|
felsabbagh3
|
0690043a43
|
Still giving sc_time_stamp error
|
2019-10-16 19:45:21 -04:00 |
|
felsabbagh3
|
8bc3b8b0a5
|
Need to link SystemC for sc_time_stamp()
|
2019-10-14 23:25:14 -04:00 |
|
Lingjun Zhu
|
5680b997b5
|
Generate LIB files for rf2_32x128_wm1
|
2019-10-14 17:08:18 -04:00 |
|
Lingjun Zhu
|
8af8c67299
|
Implemented the two-port GPR model
|
2019-10-13 19:44:50 -04:00 |
|
Lingjun Zhu
|
b9d2e09d78
|
Move the memory models from Cache_Progress to Master branch
|
2019-10-13 13:13:42 -04:00 |
|