Commit Graph

39 Commits

Author SHA1 Message Date
Blaise Tine
10e9ee124b using onehot multiplexer to reduce critical path 2021-07-08 00:26:59 -07:00
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16bef8937b adding empty to index_buffer 2021-03-30 10:15:42 -07:00
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062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
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5419859281 fcvt fix 2021-01-25 02:22:00 -08:00
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4eb85dd97a minor update 2021-01-06 23:37:24 -08:00
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146c285aa0 minor update 2021-01-06 19:59:04 -08:00
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2b8435471a speeding up simulation using dedicated full dpi-based FPU core 2021-01-06 18:44:06 -08:00
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9f128085d5 scoreboard optimization - using writeback's end-of-packet status 2020-12-30 06:47:56 -08:00
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d44144f72f FPU float<->int conversion optimization 2020-12-29 15:37:45 -08:00
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33c431ed44 multiplier unit optimization - using fifo for metadata, shift register optimization 2020-12-26 11:23:21 -08:00
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4b7d871d62 allowing partial cache request submissions, io bus support broken 2020-12-21 03:53:13 -08:00
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4bbd7bf408 performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies, 2020-12-19 02:45:06 -08:00
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13a5370254 register file refactoring 2020-12-05 01:40:50 -08:00
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97739e9dcf RAM blocks inference fixes 2020-11-30 14:02:47 -08:00
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5758ef9ebf generic_register reset network optimization 2020-11-29 18:41:36 -08:00
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ac1883a13f tabs cleanup 2020-11-28 17:08:01 -05:00
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461be0880d fixed FPU-CSR data dependence 2020-11-25 09:05:38 -08:00
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34b650be94 fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug 2020-11-17 00:27:24 -08:00
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b14007f930 pipeline optimization: fixed GPR fanout delay to execute units 2020-11-07 02:01:21 -08:00
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36ec603d17 fpga fixes: warp scheduler, fnmadd, fdiv, fsqrt 2020-09-08 07:05:26 -07:00
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49b86c4b2a SCOPE update 2020-09-05 10:52:59 -07:00
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0a45a8beb3 minor update 2020-09-01 00:56:10 -07:00
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df711986bc FPU DPI fallback 2020-08-31 09:19:55 -04:00
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0a0b28aac0 minor update - 206-214 mhz 2020-08-29 05:14:08 -07:00
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57971f6c76 decode op_mod optimization 2020-08-24 02:55:14 -07:00
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0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00
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6c12391338 pipeline refactoring - fmax >= 222 mhz 2020-08-14 21:50:14 -07:00
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65415d2bbc getting dogfood tests passing on Verilator! 2020-08-09 18:13:12 -04:00
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31ee824862 merged fpu_port branch 2020-07-31 17:13:22 -04:00
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836a735555 minor updates 2020-07-31 13:39:52 -07:00
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c9755a0c48 lkg build with pipeline + FPU fixes 2020-07-31 09:29:44 -04:00
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c2dd0a8b39 modelsim fixes && pipeline optimization 2020-07-28 14:20:23 -07:00
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8976100025 floating point support fixes 2020-07-28 04:19:46 -04:00
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f01afcc5cd floating point support fixes + riscv-tests update 2020-07-28 02:19:11 -04:00
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e0a9089647 floating point support fixes 2020-07-27 16:01:56 -04:00
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ff12393998 floating point support fixes 2020-07-27 04:53:13 -04:00
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7c86b68977 pipeline refactoring: centralized issue buffer 2020-07-26 11:21:08 -04:00
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1f63f9da25 new fpu implementation 2020-07-24 00:00:37 -04:00
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75e3c31b56 fpu implementation (part1) 2020-07-23 03:18:09 -07:00