175 lines
6.6 KiB
Verilog
175 lines
6.6 KiB
Verilog
`include "VX_define.vh"
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`include "fpnew_pkg.sv"
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`include "defs_div_sqrt_mvp.sv"
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module VX_fpu_unit #(
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parameter CORE_ID = 0
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) (
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// inputs
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input wire clk,
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input wire reset,
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// inputs
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VX_fpu_req_if fpu_req_if,
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VX_fpu_from_csr_if fpu_from_csr_if,
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// outputs
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VX_commit_fp_if fpu_commit_if,
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VX_fpu_to_csr_if fpu_to_csr_if
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);
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localparam FOP_BITS = fpnew_pkg::OP_BITS;
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localparam FMTF_BITS = $clog2(fpnew_pkg::NUM_FP_FORMATS);
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localparam FMTI_BITS = $clog2(fpnew_pkg::NUM_INT_FORMATS);
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localparam int FPU_DPATHW = `NUM_THREADS * 32;
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localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
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Width: FPU_DPATHW,
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EnableVectors: 1,
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EnableNanBox: 1,
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FpFmtMask: 5'b10000,
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IntFmtMask: 4'b0010
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};
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localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{
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PipeRegs:'{'{`LATENCY_FMULADD, 0, 0, 0, 0}, // ADDMUL
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'{default: `LATENCY_FDIVSQRT}, // DIVSQRT
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'{default: `LATENCY_FNONCOMP}, // NONCOMP
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'{default: `LATENCY_FCONV}}, // CONV
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UnitTypes:'{'{default: fpnew_pkg::PARALLEL}, // ADDMUL
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'{default: fpnew_pkg::MERGED}, // DIVSQRT
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'{default: fpnew_pkg::PARALLEL}, // NONCOMP
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'{default: fpnew_pkg::MERGED}}, // CONV
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PipeConfig: fpnew_pkg::DISTRIBUTED
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};
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wire fpu_in_ready, fpu_in_valid;
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wire fpu_out_ready, fpu_out_valid;
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wire [`LOG2UP(`FPURQ_SIZE)-1:0] fpu_in_tag, fpu_out_tag;
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wire [2:0][`NUM_THREADS-1:0][31:0] fpu_operands;
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wire [FMTF_BITS-1:0] fpu_src_fmt = fpnew_pkg::FP32;
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wire [FMTF_BITS-1:0] fpu_dst_fmt = fpnew_pkg::FP32;
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wire [FMTI_BITS-1:0] fpu_int_fmt = fpnew_pkg::INT32;
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wire [`NUM_THREADS-1:0][31:0] fpu_result;
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fpnew_pkg::status_t fpu_status;
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assign fpu_from_csr_if.warp_num = fpu_req_if.warp_num;
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wire is_dyn_rnd = &(fpu_req_if.frm);
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wire [`FRM_BITS-1:0] real_frm = is_dyn_rnd ? fpu_from_csr_if.frm : fpu_req_if.frm;
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reg [FOP_BITS-1:0] fpu_op;
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reg [`FRM_BITS-1:0] fpu_rnd;
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reg fpu_op_mod;
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always @(*) begin
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fpu_op = fpnew_pkg::SGNJ;
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fpu_op_mod = 0;
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fpu_rnd = fpu_req_if.frm;
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case (fpu_req_if.fpu_op)
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`FPU_ADD: fpu_op = fpnew_pkg::ADD;
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`FPU_SUB: begin fpu_op = fpnew_pkg::ADD; fpu_op_mod = 1; end
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`FPU_MUL: fpu_op = fpnew_pkg::MUL;
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`FPU_DIV: fpu_op = fpnew_pkg::DIV;
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`FPU_SQRT: fpu_op = fpnew_pkg::SQRT;
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`FPU_MADD: fpu_op = fpnew_pkg::FMADD;
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`FPU_MSUB: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = 1; end
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`FPU_NMSUB: fpu_op = fpnew_pkg::FNMSUB;
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`FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = 1; end
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`FPU_SGNJ: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RNE; end
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`FPU_SGNJN: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RTZ; end
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`FPU_SGNJX: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RDN; end
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`FPU_MIN: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RNE; end
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`FPU_MAX: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `FRM_RTZ; end
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`FPU_CVTWS: fpu_op = fpnew_pkg::F2I;
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`FPU_CVTWUS:begin fpu_op = fpnew_pkg::ADD; fpu_op_mod = 1; end
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`FPU_CVTSW: fpu_op = fpnew_pkg::I2F;
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`FPU_CVTSWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end
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`FPU_MVXW: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; end
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`FPU_MVWX: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `FRM_RUP; end
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`FPU_CLASS: fpu_op = fpnew_pkg::CLASSIFY;
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`FPU_CMP: fpu_op = fpnew_pkg::CMP;
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default:;
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endcase
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end
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assign fpu_operands = {fpu_req_if.rs3_data, fpu_req_if.rs2_data, fpu_req_if.rs1_data};
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fpnew_top #(
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.Features (FPU_FEATURES),
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.Implementation (FPU_IMPLEMENTATION),
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.TagType (logic [`LOG2UP(`FPURQ_SIZE)-1:0])
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) fpnew_core (
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.clk_i (clk),
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.rst_ni (1'b1),
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.operands_i (fpu_operands),
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.rnd_mode_i (fpu_rnd),
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.op_i (fpu_op),
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.op_mod_i (fpu_op_mod),
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.src_fmt_i (fpu_src_fmt),
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.dst_fmt_i (fpu_dst_fmt),
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.int_fmt_i (fpu_int_fmt),
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.vectorial_op_i (1'b1),
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.tag_i (fpu_in_tag),
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.in_valid_i (fpu_in_valid),
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.in_ready_o (fpu_in_ready),
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.flush_i (reset),
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.result_o (fpu_result),
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.status_o (fpu_status),
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.tag_o (fpu_out_tag),
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.out_valid_o (fpu_out_valid),
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.out_ready_i (fpu_out_ready),
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`UNUSED_PIN (busy_o)
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);
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wire req_push = fpu_req_if.valid && fpu_req_if.ready;
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wire req_pop = fpu_out_valid && fpu_out_ready;
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wire req_full;
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wire [`NUM_THREADS-1:0] rsp_valid;
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wire [`NW_BITS-1:0] rsp_warp_num;
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wire [31:0] rsp_curr_PC;
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wire rsp_wb;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_rd_is_fp;
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VX_index_queue #(
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.DATAW (`NUM_THREADS + `NW_BITS + 32 + 1 + `NR_BITS + 1),
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.SIZE (`FPURQ_SIZE)
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) fpu_req_queue (
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.clk (clk),
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.reset (reset),
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.write_data ({fpu_req_if.valid, fpu_req_if.warp_num, fpu_req_if.curr_PC, fpu_req_if.wb, fpu_req_if.rd, fpu_req_if.rd_is_fp}),
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.write_addr (fpu_in_tag),
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.push (req_push),
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.full (req_full),
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.pop (req_pop),
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.read_addr (fpu_out_tag),
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.read_data ({rsp_valid, rsp_warp_num, rsp_curr_PC, rsp_wb, rsp_rd, rsp_rd_is_fp}),
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`UNUSED_PIN (empty)
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);
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assign fpu_in_valid = (| fpu_req_if.valid) && ~req_full;
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assign fpu_req_if.ready = fpu_in_ready && ~req_full;
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assign fpu_commit_if.valid = rsp_valid & {`NUM_THREADS{fpu_out_valid}};
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assign fpu_commit_if.warp_num = rsp_warp_num;
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assign fpu_commit_if.curr_PC = rsp_curr_PC;
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assign fpu_commit_if.data = fpu_result;
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assign fpu_commit_if.wb = rsp_wb;
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assign fpu_commit_if.rd = rsp_rd;
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assign fpu_commit_if.rd_is_fp = rsp_rd_is_fp;
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assign fpu_out_ready = fpu_commit_if.ready;
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assign fpu_to_csr_if.valid = fpu_out_valid;
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assign fpu_to_csr_if.warp_num = rsp_warp_num;
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assign fpu_to_csr_if.fflags_NV = fpu_status.NV;
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assign fpu_to_csr_if.fflags_DZ = fpu_status.DZ;
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assign fpu_to_csr_if.fflags_OF = fpu_status.OF;
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assign fpu_to_csr_if.fflags_UF = fpu_status.UF;
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assign fpu_to_csr_if.fflags_NX = fpu_status.NX;
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endmodule |