felsabbagh3
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6779d0fade
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Instruction Multiplex LSU/EXU 1 cycle DONE
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2019-10-17 22:29:21 -04:00 |
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felsabbagh3
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95047fcadc
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Rename Stage that removes the need for forwarding
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2019-10-17 00:48:54 -04:00 |
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felsabbagh3
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8bc3b8b0a5
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Need to link SystemC for sc_time_stamp()
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2019-10-14 23:25:14 -04:00 |
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felsabbagh3
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ee83e6d8c8
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Moved GPR to back-end
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2019-10-14 19:08:32 -04:00 |
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felsabbagh3
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e67310acfb
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New Warp Scheduler + VCD Enable
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2019-09-15 00:12:41 -04:00 |
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felsabbagh3
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3c3a443bd5
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New RF with Evaluation
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2019-09-11 01:04:23 -04:00 |
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felsabbagh3
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8d143d7739
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Quartus + GPR evaluation
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2019-09-10 20:23:01 -04:00 |
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felsabbagh3
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ac9b06bf7d
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Before FE BE abstraction
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2019-09-08 16:21:37 -04:00 |
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felsabbagh3
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fe09aafbb4
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Interface Checkpoint 2 - Remove Lints
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2019-09-05 19:32:37 -04:00 |
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Hyesoon Kim
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6b3b124a30
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fix typo of std=c++11
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2019-06-12 07:32:20 -04:00 |
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felsabbagh3
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9cd8ee8579
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Added std=c++11
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2019-06-11 23:21:48 -07:00 |
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felsabbagh3
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c83ef94d02
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1 WARP 2 THREADS WORKING
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2019-03-31 05:02:55 -04:00 |
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felsabbagh3
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cc0fb0eece
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better use of valid signal
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2019-03-27 00:07:59 -04:00 |
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felsabbagh3
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7a528c5ef2
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Packing data wires + ALU module
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2019-03-26 19:17:11 -04:00 |
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felsabbagh3
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01d142c6e6
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rtl passing all tests
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2019-03-22 02:44:53 -04:00 |
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felsabbagh3
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656475b3b3
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Passing Most tests
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2019-03-21 23:47:48 -04:00 |
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felsabbagh3
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d08d389177
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Started on rtl (Finished till decode)
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2019-03-21 02:23:10 -04:00 |
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