wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
1,563 Commits 9 Branches 0 Tags
638614fd6d56f9c798e958703e7190f49c485ecb
Commit Graph
15 Commits
Author SHA1 Message Date
Blaise Tine 062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
Blaise Tine 3f5fd6d394 using shiftreg-based skid buffers 2021-02-28 02:20:09 -08:00
Blaise Tine e64996946d using 44-bit perf counters - aligned with DSP counters width 2021-02-28 02:05:47 -08:00
Blaise Tine 700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
Blaise Tine 1346d64ba9 minor update 2021-02-22 04:04:13 -08:00
Blaise Tine 7560202f8b cache bank refactoring - removing unecessary core response fifo & restoring single port data access 2021-02-21 21:47:46 -08:00
Blaise Tine ab63ac9e5d cache request interfaces update 2021-02-10 20:55:04 -08:00
Blaise Tine 665b97b810 multi-ported cache support for streaming 2021-02-08 16:13:32 -08:00
Blaise Tine 62ff97d6e1 minor update - smem perf update 2021-02-01 10:29:20 -08:00
Blaise Tine 8775f63ec4 lkg build rollout with 16cores optimization on arria10 2021-01-24 16:49:22 -08:00
Blaise Tine a046bd7a73 cache pipeline optimization 2021-01-17 17:19:52 -08:00
Blaise Tine ed216ab39d minor updates 2021-01-17 13:58:43 -08:00
Blaise Tine 5b80484123 minor updates 2021-01-16 14:16:10 -08:00
Blaise Tine a56ecb696d minor updates 2021-01-16 14:05:47 -08:00
Blaise Tine fcbf57b66a specialized shared memory module 2021-01-16 04:41:58 -08:00