Lingjun Zhu
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405926f66f
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Generated memory blocks for data cache (data), data cache (tag), shared memory
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2019-10-20 14:52:28 -04:00 |
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Lingjun Zhu
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93531715bb
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Created a testbench and simulated the read/write of the register file
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2019-10-18 22:55:34 -04:00 |
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Lingjun Zhu
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84d321a517
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Create the memory blocks with CLN28HPM
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2019-10-17 15:38:48 -04:00 |
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felsabbagh3
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9a9afbbb6b
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Updated makefile
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2019-10-16 19:56:11 -04:00 |
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felsabbagh3
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0690043a43
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Still giving sc_time_stamp error
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2019-10-16 19:45:21 -04:00 |
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felsabbagh3
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8bc3b8b0a5
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Need to link SystemC for sc_time_stamp()
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2019-10-14 23:25:14 -04:00 |
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Lingjun Zhu
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5680b997b5
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Generate LIB files for rf2_32x128_wm1
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2019-10-14 17:08:18 -04:00 |
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Lingjun Zhu
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8af8c67299
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Implemented the two-port GPR model
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2019-10-13 19:44:50 -04:00 |
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Lingjun Zhu
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b9d2e09d78
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Move the memory models from Cache_Progress to Master branch
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2019-10-13 13:13:42 -04:00 |
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