Commit Graph

24 Commits

Author SHA1 Message Date
Blaise Tine
87888a9a93 master merge fixes 2021-04-04 21:12:12 -07:00
Blaise Tine
09dbeacc14 minor update 2021-03-22 23:04:35 -07:00
Blaise Tine
859877a00d tex_unit partial update 2021-03-20 08:40:57 -04:00
Krishna Yalamarthy
7587876820 Texture Instruction - Fixed Color 2021-03-15 16:41:28 -04:00
Blaise Tine
10a994d11a csr minor update 2021-03-08 03:46:07 -08:00
Blaise Tine
b441870789 rename use_imm and use_PC 2021-03-01 00:38:46 -08:00
Blaise Tine
3f5fd6d394 using shiftreg-based skid buffers 2021-02-28 02:20:09 -08:00
Blaise Tine
700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
Blaise Tine
6739dc7923 minor update - registering execute units skid buffers 2021-02-21 15:11:08 -08:00
Blaise Tine
8775f63ec4 lkg build rollout with 16cores optimization on arria10 2021-01-24 16:49:22 -08:00
Blaise Tine
98945df5ae minor updates 2021-01-17 12:50:07 -08:00
Blaise Tine
7c4823e65c fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests 2021-01-11 23:55:09 -08:00
Blaise Tine
d44144f72f FPU float<->int conversion optimization 2020-12-29 15:37:45 -08:00
Blaise Tine
3e9abb978b fixed typo 2020-12-09 13:03:22 -08:00
Blaise Tine
e0905f8352 minor update 2020-12-09 05:34:27 -08:00
Blaise Tine
13a5370254 register file refactoring 2020-12-05 01:40:50 -08:00
Blaise Tine
fceb561cbd synchronous reset network optimization: only reset register when required 2020-11-11 20:54:54 -08:00
Blaise Tine
b14007f930 pipeline optimization: fixed GPR fanout delay to execute units 2020-11-07 02:01:21 -08:00
Blaise Tine
49b86c4b2a SCOPE update 2020-09-05 10:52:59 -07:00
Blaise Tine
af84e01856 minor update 2020-08-31 06:17:49 -07:00
Blaise Tine
fde3f46798 ibuffer optimization 2020-08-26 04:44:36 -07:00
Blaise Tine
b211b29670 removing pipeline additional registers 2020-08-25 14:02:35 -07:00
Blaise Tine
57971f6c76 decode op_mod optimization 2020-08-24 02:55:14 -07:00
Blaise Tine
0b355f228e ibuffer addition 2020-08-22 00:22:04 -07:00