SystemVerilog tweaks to appease Quartus and make Quartus synthesis work

rtl/cache/VX_Cache_Bank.v

@@ -201,7 +201,8 @@ module VX_Cache_Bank
     wire[NUM_WORDS_PER_BLOCK-1:0][3:0]  we;
     wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
     genvar g; 
-    for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin
+	 generate
+    for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin : write_enables
         wire normal_write = (read_or_write  && ((access && (block_offset == g))) && !miss);
 
         assign we[g]      = (write_from_mem)     ? 4'b1111  : 
@@ -215,6 +216,7 @@ module VX_Cache_Bank
         assign data_write[g] = write_from_mem ? fetched_writedata[g] : use_write_data;
         assign way_to_update = evicted_way;
     end
+	 endgenerate
 
 
     VX_cache_data_per_index #(

rtl/cache/VX_cache_data_per_index.v

@@ -59,6 +59,7 @@ module VX_cache_data_per_index
     localparam SEND_MEM_REQ  = 1; // Write back this block into memory
     localparam RECIV_MEM_RSP = 2;
 
+	 generate
     if(CACHE_WAYS != 1) begin
         VX_generic_priority_encoder #(.N(CACHE_WAYS)) valid_index
         (
@@ -79,6 +80,7 @@ module VX_cache_data_per_index
       assign invalid_found = (valid_use_per_way == 1'b0) ? 1 : 0;
       assign invalid_index = 0;
     end
+	 endgenerate
 
 
 
@@ -105,6 +107,7 @@ module VX_cache_data_per_index
 
 
     genvar ways;
+	 generate
 	  for(ways=0; ways < CACHE_WAYS; ways = ways + 1) begin : each_way
 
 
@@ -144,6 +147,7 @@ module VX_cache_data_per_index
 	        .dirty_use (dirty_use_per_way[ways])
 	    );
 	  end
+	  endgenerate
 
     // always @(posedge clk or posedge rst) begin
     //   if (rst) begin

rtl/cache/VX_d_cache.v

@@ -161,8 +161,8 @@ module VX_d_cache
     reg[NUM_REQ-1:0] debug_hit_per_bank_mask[CACHE_BANKS-1:0];
 
     genvar bid;
-    for (bid = 0; bid < CACHE_BANKS; bid=bid+1)
-    begin
+	 generate
+    for (bid = 0; bid < CACHE_BANKS; bid=bid+1) begin : chooose_threads
       wire[NUM_REQ-1:0]        use_threads_track_banks = thread_track_banks[bid];
       wire[LOG_NUM_REQ-1:0] use_thread_index        = index_per_bank[bid];
       wire                  use_write_final_data    = hit_per_bank[bid];
@@ -177,6 +177,7 @@ module VX_d_cache
         assign debug_hit_per_bank_mask[bid]   = {NUM_REQ{hit_per_bank[bid]}};
         assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid];
     end
+	 endgenerate
 
     integer test_bid;
     always @(*) begin
@@ -207,10 +208,11 @@ module VX_d_cache
 
 
     genvar tid;
-    for (tid = 0; tid < NUM_REQ; tid =tid+1)
-    begin
+	 generate
+    for (tid = 0; tid < NUM_REQ; tid =tid+1) begin : new_final_data_read_Qual_setup
       assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid];
     end
+	 endgenerate
 
 
     assign detect_bank_miss = (valid_per_bank & ~hit_per_bank);
@@ -293,8 +295,7 @@ module VX_d_cache
 
   genvar bank_id;
   generate
-    for (bank_id = 0; bank_id < CACHE_BANKS; bank_id = bank_id + 1)
-      begin
+    for (bank_id = 0; bank_id < CACHE_BANKS; bank_id = bank_id + 1) begin : cache_banks
         wire[31:0] bank_addr    = (state == SEND_MEM_REQ)  ? miss_addr  :
                                   (state == RECIV_MEM_RSP) ? miss_addr   :
                                   i_p_addr[send_index_to_bank[bank_id]];

rtl/cache/VX_d_cache_encapsulate.v

@@ -65,27 +65,25 @@ module VX_d_cache_encapsulate (
     wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter;
 
 
-    genvar curr_thraed;
-    for (curr_thraed = 0; curr_thraed < `NT; curr_thraed = curr_thraed + 1) begin
+    genvar curr_thraed, curr_bank, curr_word;
+	 generate
+    for (curr_thraed = 0; curr_thraed < `NT; curr_thraed = curr_thraed + 1) begin : threads
     	assign i_p_valid_inter[curr_thraed]                = i_p_valid[curr_thraed];
     	assign i_p_addr_inter[curr_thraed]                 = i_p_addr[curr_thraed];
     	assign i_p_writedata_inter[curr_thraed]            = i_p_writedata[curr_thraed];
     	assign o_p_readdata[curr_thraed]       = o_p_readdata_inter[curr_thraed];
     	assign o_p_readdata_valid[curr_thraed] = o_p_readdata_valid_inter[curr_thraed];
     end
-
-
-    genvar curr_bank;
-    genvar curr_word;
-    for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin
-
-    	for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
+	 
+    for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin : banks
+    	for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : words
 
     		assign o_m_writedata[curr_bank][curr_word] = o_m_writedata_inter[curr_bank][curr_word];
     		assign i_m_readdata_inter[curr_bank][curr_word]        = i_m_readdata[curr_bank][curr_word];
 
     	end
     end
+	 endgenerate
 
 VX_d_cache dcache(
 	.clk                (clk),