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cache refactoring

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This commit is contained in:
Blaise Tine
2021-01-17 00:18:56 -08:00
parent 5b80484123
commit d4e7b28be8
12 changed files with 189 additions and 332 deletions
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4
hw/rtl/cache/VX_cache.v vendored
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@@ -29,9 +29,6 @@ module VX_cache #(
// Enable cache writeable
parameter WRITE_ENABLE = 1,
// Enable write-through
parameter WRITE_THROUGH = 1,
// core request tag size
parameter CORE_TAG_WIDTH = $clog2(MSHR_SIZE),
@@ -242,7 +239,6 @@ module VX_cache #(
.CRSQ_SIZE (CRSQ_SIZE),
.DREQ_SIZE (DREQ_SIZE),
.WRITE_ENABLE (WRITE_ENABLE),
.WRITE_THROUGH (WRITE_THROUGH),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
.BANK_ADDR_OFFSET (BANK_ADDR_OFFSET)