interfaces refactoring
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@@ -5,6 +5,9 @@
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interface VX_backend_req_if ();
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wire [`NUM_THREADS-1:0] valid;
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wire [`NW_BITS-1:0] warp_num;
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wire [31:0] curr_PC;
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wire [11:0] csr_address;
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wire is_csr;
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wire csr_immed;
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@@ -20,14 +23,11 @@ interface VX_backend_req_if ();
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wire [`BYTE_EN_BITS-1:0] mem_write;
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wire [2:0] branch_type;
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wire [19:0] upper_immed;
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wire [31:0] curr_PC;
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wire is_etype;
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wire is_jal;
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wire jal;
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wire [31:0] jal_offset;
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wire [31:0] next_PC;
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wire [`NUM_THREADS-1:0] valid;
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wire [`NW_BITS-1:0] warp_num;
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wire [31:0] next_PC;
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// GPGPU stuff
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wire is_wspawn;
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@@ -8,7 +8,7 @@ interface VX_branch_rsp_if ();
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wire valid_branch;
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wire branch_dir;
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wire [31:0] branch_dest;
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wire [`NW_BITS-1:0] branch_warp_num;
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wire [`NW_BITS-1:0] warp_num;
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endinterface
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@@ -10,13 +10,13 @@ interface VX_cache_core_req_if #(
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parameter CORE_TAG_ID_BITS = 0
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) ();
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wire [NUM_REQUESTS-1:0] core_req_valid;
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wire [NUM_REQUESTS-1:0] core_req_rw;
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wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] core_req_byteen;
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wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr;
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wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data;
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wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag;
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wire core_req_ready;
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wire [NUM_REQUESTS-1:0] valid;
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wire [NUM_REQUESTS-1:0] rw;
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wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] byteen;
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wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] addr;
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wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] data;
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wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag;
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wire ready;
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endinterface
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@@ -10,10 +10,10 @@ interface VX_cache_core_rsp_if #(
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parameter CORE_TAG_ID_BITS = 0
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) ();
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wire [NUM_REQUESTS-1:0] core_rsp_valid;
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wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data;
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wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag;
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wire core_rsp_ready;
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wire [NUM_REQUESTS-1:0] valid;
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wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] data;
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wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag;
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wire ready;
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endinterface
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@@ -9,13 +9,13 @@ interface VX_cache_dram_req_if #(
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parameter DRAM_TAG_WIDTH = 1
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) ();
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wire dram_req_valid;
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wire dram_req_rw;
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wire [(DRAM_LINE_WIDTH/8)-1:0] dram_req_byteen;
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wire [DRAM_ADDR_WIDTH-1:0] dram_req_addr;
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wire [DRAM_LINE_WIDTH-1:0] dram_req_data;
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wire [DRAM_TAG_WIDTH-1:0] dram_req_tag;
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wire dram_req_ready;
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wire valid;
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wire rw;
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wire [(DRAM_LINE_WIDTH/8)-1:0] byteen;
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wire [DRAM_ADDR_WIDTH-1:0] addr;
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wire [DRAM_LINE_WIDTH-1:0] data;
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wire [DRAM_TAG_WIDTH-1:0] tag;
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wire ready;
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endinterface
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@@ -8,10 +8,10 @@ interface VX_cache_dram_rsp_if #(
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parameter DRAM_TAG_WIDTH = 1
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) ();
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wire dram_rsp_valid;
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wire [DRAM_LINE_WIDTH-1:0] dram_rsp_data;
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wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag;
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wire dram_rsp_ready;
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wire valid;
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wire [DRAM_LINE_WIDTH-1:0] data;
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wire [DRAM_TAG_WIDTH-1:0] tag;
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wire ready;
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endinterface
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@@ -8,11 +8,11 @@ interface VX_cache_snp_req_if #(
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parameter SNP_TAG_WIDTH = 0
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) ();
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wire snp_req_valid;
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wire [DRAM_ADDR_WIDTH-1:0] snp_req_addr;
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wire snp_req_invalidate;
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wire [SNP_TAG_WIDTH-1:0] snp_req_tag;
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wire snp_req_ready;
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wire valid;
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wire [DRAM_ADDR_WIDTH-1:0] addr;
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wire invalidate;
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wire [SNP_TAG_WIDTH-1:0] tag;
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wire ready;
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endinterface
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@@ -7,9 +7,9 @@ interface VX_cache_snp_rsp_if #(
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parameter SNP_TAG_WIDTH = 0
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) ();
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wire snp_rsp_valid;
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wire [SNP_TAG_WIDTH-1:0] snp_rsp_tag;
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wire snp_rsp_ready;
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wire valid;
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wire [SNP_TAG_WIDTH-1:0] tag;
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wire ready;
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endinterface
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@@ -5,10 +5,10 @@
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interface VX_inst_meta_if ();
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wire [31:0] instruction;
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wire [31:0] inst_pc;
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wire [`NW_BITS-1:0] warp_num;
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wire [`NUM_THREADS-1:0] valid;
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wire [31:0] curr_PC;
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wire [`NW_BITS-1:0] warp_num;
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wire [31:0] instruction;
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endinterface
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@@ -8,7 +8,7 @@ interface VX_jal_rsp_if ();
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wire jal;
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wire [31:0] jal_dest;
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wire [`NW_BITS-1:0] jal_warp_num;
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wire [`NW_BITS-1:0] warp_num;
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endinterface
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@@ -7,7 +7,7 @@
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interface VX_join_if ();
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wire is_join;
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wire [`NW_BITS-1:0] join_warp_num;
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wire [`NW_BITS-1:0] warp_num;
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endinterface
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