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debug tracing refactoring

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Blaise Tine
2021-10-17 13:42:16 -07:00
parent af6d9e7a8b
commit bf72800676
26 changed files with 148 additions and 169 deletions
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2
hw/rtl/cache/VX_data_access.sv vendored
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@@ -119,7 +119,7 @@ module VX_data_access #(
`UNUSED_VAR (stall)
`ifdef DBG_PRINT_CACHE_DATA
`ifdef DBG_TRACE_CACHE_DATA
always @(posedge clk) begin
if (fill && ~stall) begin
dpi_trace("%d: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, fill_data);