diff --git a/hw/rtl/VX_alu_unit.sv b/hw/rtl/VX_alu_unit.sv index 129b1202..8840f044 100644 --- a/hw/rtl/VX_alu_unit.sv +++ b/hw/rtl/VX_alu_unit.sv @@ -217,7 +217,7 @@ module VX_alu_unit #( // can accept new request? assign alu_req_if.ready = ready_in; -`ifdef DBG_PRINT_PIPELINE +`ifdef DBG_TRACE_PIPELINE always @(posedge clk) begin if (branch_ctl_if.valid) begin dpi_trace("%d: core%0d-branch: wid=%0d, PC=%0h, taken=%b, dest=%0h\n", diff --git a/hw/rtl/VX_commit.sv b/hw/rtl/VX_commit.sv index 8d25fae0..07b83df0 100644 --- a/hw/rtl/VX_commit.sv +++ b/hw/rtl/VX_commit.sv @@ -85,7 +85,7 @@ module VX_commit #( // store and gpu commits don't writeback assign st_commit_if.ready = 1'b1; -`ifdef DBG_PRINT_PIPELINE +`ifdef DBG_TRACE_PIPELINE always @(posedge clk) begin if (alu_commit_if.valid && alu_commit_if.ready) begin dpi_trace("%d: core%0d-commit: wid=%0d, PC=%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, data=", $time, CORE_ID, alu_commit_if.wid, alu_commit_if.PC, alu_commit_if.tmask, alu_commit_if.wb, alu_commit_if.rd); diff --git a/hw/rtl/VX_decode.sv b/hw/rtl/VX_decode.sv index 4ac6fe13..c2a6cac8 100644 --- a/hw/rtl/VX_decode.sv +++ b/hw/rtl/VX_decode.sv @@ -1,6 +1,6 @@ `include "VX_define.vh" -`ifdef DBG_PRINT_PIPELINE -`include "VX_print_instr.vh" +`ifdef DBG_TRACE_PIPELINE +`include "VX_trace_instr.vh" `endif `ifdef EXT_F_ENABLE @@ -427,13 +427,13 @@ module VX_decode #( assign ifetch_rsp_if.ready = decode_if.ready; -`ifdef DBG_PRINT_PIPELINE +`ifdef DBG_TRACE_PIPELINE always @(posedge clk) begin if (decode_if.valid && decode_if.ready) begin dpi_trace("%d: core%0d-decode: wid=%0d, PC=%0h, ex=", $time, CORE_ID, decode_if.wid, decode_if.PC); - print_ex_type(decode_if.ex_type); + trace_ex_type(decode_if.ex_type); dpi_trace(", op="); - print_ex_op(decode_if.ex_type, decode_if.op_type, decode_if.op_mod); + trace_ex_op(decode_if.ex_type, decode_if.op_type, decode_if.op_mod); dpi_trace(", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=%0h, use_pc=%b, use_imm=%b\n", decode_if.op_mod, decode_if.tmask, decode_if.wb, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.rs3, decode_if.imm, decode_if.use_PC, decode_if.use_imm); end end diff --git a/hw/rtl/VX_icache_stage.sv b/hw/rtl/VX_icache_stage.sv index 96ab2531..cb33b82d 100644 --- a/hw/rtl/VX_icache_stage.sv +++ b/hw/rtl/VX_icache_stage.sv @@ -88,7 +88,7 @@ module VX_icache_stage #( `SCOPE_ASSIGN (icache_rsp_data, icache_rsp_if.data); `SCOPE_ASSIGN (icache_rsp_tag, rsp_tag); -`ifdef DBG_PRINT_CORE_ICACHE +`ifdef DBG_TRACE_CORE_ICACHE always @(posedge clk) begin if (icache_req_if.valid && icache_req_if.ready) begin dpi_trace("%d: I$%0d req: wid=%0d, PC=%0h\n", $time, CORE_ID, ifetch_req_if.wid, ifetch_req_if.PC); diff --git a/hw/rtl/VX_issue.sv b/hw/rtl/VX_issue.sv index 04f8788b..65b3a8d8 100644 --- a/hw/rtl/VX_issue.sv +++ b/hw/rtl/VX_issue.sv @@ -204,7 +204,7 @@ module VX_issue #( `endif `endif -`ifdef DBG_PRINT_PIPELINE +`ifdef DBG_TRACE_PIPELINE always @(posedge clk) begin if (alu_req_if.valid && alu_req_if.ready) begin dpi_trace("%d: core%0d-issue: wid=%0d, PC=%0h, ex=ALU, tmask=%b, rd=%0d, rs1_data=", diff --git a/hw/rtl/VX_lsu_unit.sv b/hw/rtl/VX_lsu_unit.sv index 11457d2f..6788a76e 100644 --- a/hw/rtl/VX_lsu_unit.sv +++ b/hw/rtl/VX_lsu_unit.sv @@ -330,7 +330,7 @@ module VX_lsu_unit #( end `endif -`ifdef DBG_PRINT_CORE_DCACHE +`ifdef DBG_TRACE_CORE_DCACHE wire dcache_req_fire_any = (| dcache_req_fire); always @(posedge clk) begin if (lsu_req_if.valid && fence_wait) begin diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index 38ccd4fa..908428b7 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -123,27 +123,6 @@ `define LTRIM(x, s) x[s-1:0] -`define PRINT_ARRAY1D(a, m) \ - $write("{"); \ - for (integer i = (m-1); i >= 0; --i) begin \ - if (i != (m-1)) $write(", "); \ - $write("0x%0h", a[i]); \ - end \ - $write("}"); \ - -`define PRINT_ARRAY2D(a, m, n) \ - $write("{"); \ - for (integer i = n-1; i >= 0; --i) begin \ - if (i != (n-1)) $write(", "); \ - $write("{"); \ - for (integer j = (m-1); j >= 0; --j) begin \ - if (j != (m-1)) $write(", "); \ - $write("0x%0h", a[i][j]); \ - end \ - $write("}"); \ - end \ - $write("}") - `define TRACE_ARRAY1D(a, m) \ dpi_trace("{"); \ for (integer i = (m-1); i >= 0; --i) begin \ diff --git a/hw/rtl/VX_scoreboard.sv b/hw/rtl/VX_scoreboard.sv index 9503ecdf..4dec1aaf 100644 --- a/hw/rtl/VX_scoreboard.sv +++ b/hw/rtl/VX_scoreboard.sv @@ -57,7 +57,7 @@ module VX_scoreboard #( if (reset) begin deadlock_ctr <= 0; end else begin - `ifdef DBG_PRINT_PIPELINE + `ifdef DBG_TRACE_PIPELINE if (ibuffer_if.valid && ~ibuffer_if.ready) begin dpi_trace("%d: *** core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b\n", $time, CORE_ID, ibuffer_if.wid, ibuffer_if.PC, ibuffer_if.rd, ibuffer_if.wb, diff --git a/hw/rtl/VX_print_instr.vh b/hw/rtl/VX_trace_instr.vh similarity index 98% rename from hw/rtl/VX_print_instr.vh rename to hw/rtl/VX_trace_instr.vh index 5b9aa63a..e228179e 100644 --- a/hw/rtl/VX_print_instr.vh +++ b/hw/rtl/VX_trace_instr.vh @@ -1,9 +1,9 @@ -`ifndef VX_PRINT_INSTR -`define VX_PRINT_INSTR +`ifndef VX_TRACE_INSTR +`define VX_TRACE_INSTR `include "VX_define.vh" -task print_ex_type ( +task trace_ex_type ( input [`EX_BITS-1:0] ex_type ); case (ex_type) @@ -16,7 +16,7 @@ task print_ex_type ( endcase endtask -task print_ex_op ( +task trace_ex_op ( input [`EX_BITS-1:0] ex_type, input [`INST_OP_BITS-1:0] op_type, input [`INST_MOD_BITS-1:0] op_mod diff --git a/hw/rtl/Vortex.sv b/hw/rtl/Vortex.sv index 03469568..96b5602b 100644 --- a/hw/rtl/Vortex.sv +++ b/hw/rtl/Vortex.sv @@ -201,7 +201,7 @@ module Vortex ( `SCOPE_ASSIGN (mem_rsp_tag, mem_rsp_tag); `SCOPE_ASSIGN (busy, busy); -`ifdef DBG_PRINT_MEM +`ifdef DBG_TRACE_MEM always @(posedge clk) begin if (mem_req_valid && mem_req_ready) begin if (mem_req_rw) diff --git a/hw/rtl/afu/VX_avs_wrapper.sv b/hw/rtl/afu/VX_avs_wrapper.sv index d6aaf890..755cdf05 100644 --- a/hw/rtl/afu/VX_avs_wrapper.sv +++ b/hw/rtl/afu/VX_avs_wrapper.sv @@ -158,7 +158,7 @@ module VX_avs_wrapper #( .ready_out (mem_rsp_ready) ); -`ifdef DBG_PRINT_AVS +`ifdef DBG_TRACE_AVS always @(posedge clk) begin if (mem_req_valid && mem_req_ready) begin if (mem_req_rw) begin diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index adee880f..22d1ec29 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -187,36 +187,36 @@ always @(posedge clk) begin case (mmio_hdr.address) MMIO_IO_ADDR: begin cmd_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data); - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: MMIO_IO_ADDR: addr=%0h, data=0x%0h\n", $time, mmio_hdr.address, t_ccip_clAddr'(cp2af_sRxPort.c0.data)); `endif end MMIO_MEM_ADDR: begin cmd_mem_addr <= $bits(cmd_mem_addr)'(cp2af_sRxPort.c0.data); - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: MMIO_MEM_ADDR: addr=%0h, data=0x%0h\n", $time, mmio_hdr.address, $bits(cmd_mem_addr)'(cp2af_sRxPort.c0.data)); `endif end MMIO_DATA_SIZE: begin cmd_data_size <= $bits(cmd_data_size)'(cp2af_sRxPort.c0.data); - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: MMIO_DATA_SIZE: addr=%0h, data=%0d\n", $time, mmio_hdr.address, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); `endif end MMIO_CMD_TYPE: begin - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: MMIO_CMD_TYPE: addr=%0h, data=%0d\n", $time, mmio_hdr.address, $bits(cmd_type)'(cp2af_sRxPort.c0.data)); `endif end `ifdef SCOPE MMIO_SCOPE_WRITE: begin - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: MMIO_SCOPE_WRITE: addr=%0h, data=%0h\n", $time, mmio_hdr.address, 64'(cp2af_sRxPort.c0.data)); `endif end `endif default: begin - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: Unknown MMIO Wr: addr=%0h, data=%0h\n", $time, mmio_hdr.address, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); `endif end @@ -243,7 +243,7 @@ always @(posedge clk) begin 16'h0008: mmio_tx.data <= 64'h0; // reserved MMIO_STATUS: begin mmio_tx.data <= 64'({cout_q_dout, !cout_q_empty, 8'(state)}); - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE if (state != STATE_WIDTH'(mmio_tx.data)) begin dpi_trace("%d: MMIO_STATUS: addr=%0h, state=%0d\n", $time, mmio_hdr.address, state); end @@ -252,20 +252,20 @@ always @(posedge clk) begin `ifdef SCOPE MMIO_SCOPE_READ: begin mmio_tx.data <= cmd_scope_rdata; - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: MMIO_SCOPE_READ: addr=%0h, data=%0h\n", $time, mmio_hdr.address, cmd_scope_rdata); `endif end `endif MMIO_DEV_CAPS: begin mmio_tx.data <= dev_caps; - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: MMIO_DEV_CAPS: addr=%0h, data=%0h\n", $time, mmio_hdr.address, dev_caps); `endif end default: begin mmio_tx.data <= 64'h0; - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: Unknown MMIO Rd: addr=%0h\n", $time, mmio_hdr.address); `endif end @@ -299,19 +299,19 @@ always @(posedge clk) begin STATE_IDLE: begin case (cmd_type) CMD_MEM_READ: begin - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: STATE READ: ia=%0h addr=%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); `endif state <= STATE_READ; end CMD_MEM_WRITE: begin - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: STATE WRITE: ia=%0h addr=%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); `endif state <= STATE_WRITE; end CMD_RUN: begin - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: STATE START\n", $time); `endif vx_reset <= 1; @@ -326,7 +326,7 @@ always @(posedge clk) begin STATE_READ: begin if (cmd_read_done) begin state <= STATE_IDLE; - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: STATE IDLE\n", $time); `endif end @@ -335,7 +335,7 @@ always @(posedge clk) begin STATE_WRITE: begin if (cmd_write_done) begin state <= STATE_IDLE; - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: STATE IDLE\n", $time); `endif end @@ -347,7 +347,7 @@ always @(posedge clk) begin if (cmd_run_done) begin vx_started <= 0; state <= STATE_IDLE; - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: STATE IDLE\n", $time); `endif end @@ -701,7 +701,7 @@ always @(posedge clk) begin if (cci_rd_req_fire) begin cci_rd_req_addr <= cci_rd_req_addr + 1; cci_rd_req_ctr <= cci_rd_req_ctr + 1; - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: CCI Rd Req: addr=%0h, tag=%0h, rem=%0d, pending=%0d\n", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr - 1), cci_pending_reads); `endif end @@ -711,13 +711,13 @@ always @(posedge clk) begin if (CCI_RD_QUEUE_TAGW'(cci_rd_rsp_ctr) == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin cci_mem_wr_req_addr_base <= cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE); end - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: CCI Rd Rsp: idx=%0d, ctr=%0d, data=%0h\n", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, cp2af_sRxPort.c0.data); `endif end if (cci_rdq_pop) begin - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: CCI Rd Queue Pop: pending=%0d\n", $time, cci_pending_reads); `endif end @@ -858,13 +858,13 @@ begin if (cci_wr_req_ctr == CCI_ADDR_WIDTH'(1)) begin cci_wr_req_done <= 1; end - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: CCI Wr Req: addr=%0h, rem=%0d, pending=%0d, data=%0h\n", $time, cci_wr_req_addr, (cci_wr_req_ctr - 1), cci_pending_writes, af2cp_sTxPort.c1.data); `endif end if (cci_wr_rsp_fire) begin - `ifdef DBG_PRINT_OPAE + `ifdef DBG_TRACE_OPAE dpi_trace("%d: CCI Wr Rsp: pending=%0d\n", $time, cci_pending_writes); `endif end diff --git a/hw/rtl/cache/VX_bank.sv b/hw/rtl/cache/VX_bank.sv index 1f05ae04..14d50e29 100644 --- a/hw/rtl/cache/VX_bank.sv +++ b/hw/rtl/cache/VX_bank.sv @@ -509,7 +509,7 @@ module VX_bank #( assign perf_mshr_stalls = mshr_alm_full; `endif -`ifdef DBG_PRINT_CACHE_BANK +`ifdef DBG_TRACE_CACHE_BANK wire crsq_fire = crsq_valid && crsq_ready; wire pipeline_stall = (mshr_valid || mem_rsp_valid || creq_valid) && ~(mshr_fire || mem_rsp_fire || creq_fire); diff --git a/hw/rtl/cache/VX_data_access.sv b/hw/rtl/cache/VX_data_access.sv index 5b81140d..a1a5247b 100644 --- a/hw/rtl/cache/VX_data_access.sv +++ b/hw/rtl/cache/VX_data_access.sv @@ -119,7 +119,7 @@ module VX_data_access #( `UNUSED_VAR (stall) -`ifdef DBG_PRINT_CACHE_DATA +`ifdef DBG_TRACE_CACHE_DATA always @(posedge clk) begin if (fill && ~stall) begin dpi_trace("%d: cache%0d:%0d data-fill: addr=%0h, blk_addr=%0d, data=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, fill_data); diff --git a/hw/rtl/cache/VX_miss_resrv.sv b/hw/rtl/cache/VX_miss_resrv.sv index 152a6702..bda63bb1 100644 --- a/hw/rtl/cache/VX_miss_resrv.sv +++ b/hw/rtl/cache/VX_miss_resrv.sv @@ -202,7 +202,7 @@ module VX_miss_resrv #( `UNUSED_VAR (lookup_valid) -`ifdef DBG_PRINT_CACHE_MSHR +`ifdef DBG_TRACE_CACHE_MSHR always @(posedge clk) begin if (allocate_fire || fill_valid || dequeue_fire || lookup_replay || lookup_valid || release_valid) begin if (allocate_fire) diff --git a/hw/rtl/cache/VX_shared_mem.sv b/hw/rtl/cache/VX_shared_mem.sv index 51c60a38..f3af3139 100644 --- a/hw/rtl/cache/VX_shared_mem.sv +++ b/hw/rtl/cache/VX_shared_mem.sv @@ -271,7 +271,7 @@ module VX_shared_mem #( end `endif -`ifdef DBG_PRINT_CACHE_BANK +`ifdef DBG_TRACE_CACHE_BANK reg is_multi_tag_req; `IGNORE_UNUSED_BEGIN diff --git a/hw/rtl/cache/VX_tag_access.sv b/hw/rtl/cache/VX_tag_access.sv index e3433528..55124a65 100644 --- a/hw/rtl/cache/VX_tag_access.sv +++ b/hw/rtl/cache/VX_tag_access.sv @@ -61,7 +61,7 @@ module VX_tag_access #( `UNUSED_VAR (stall) -`ifdef DBG_PRINT_CACHE_TAG +`ifdef DBG_TRACE_CACHE_TAG always @(posedge clk) begin if (fill && ~stall) begin dpi_trace("%d: cache%0d:%0d tag-fill: addr=%0h, blk_addr=%0d, tag_id=%0h\n", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr, BANK_ID), line_addr, line_tag); diff --git a/hw/rtl/libs/VX_scope.sv b/hw/rtl/libs/VX_scope.sv index 051bdb58..2cd8798b 100644 --- a/hw/rtl/libs/VX_scope.sv +++ b/hw/rtl/libs/VX_scope.sv @@ -93,13 +93,13 @@ module VX_scope #( CMD_SET_START: begin delay_val <= $bits(delay_val)'(cmd_data); cmd_start <= 1; - `ifdef DBG_PRINT_SCOPE + `ifdef DBG_TRACE_SCOPE dpi_trace("%d: *** scope: CMD_SET_START: delay_val=%0d\n", $time, $bits(delay_val)'(cmd_data)); `endif end CMD_SET_STOP: begin waddr_end <= $bits(waddr)'(cmd_data); - `ifdef DBG_PRINT_SCOPE + `ifdef DBG_TRACE_SCOPE dpi_trace("%d: *** scope: CMD_SET_STOP: waddr_end=%0d\n", $time, $bits(waddr)'(cmd_data)); `endif end @@ -116,7 +116,7 @@ module VX_scope #( delta <= 0; delay_cntr <= 0; start_time <= timestamp; - `ifdef DBG_PRINT_SCOPE + `ifdef DBG_TRACE_SCOPE dpi_trace("%d: *** scope: recording start - start_time=%0d\n", $time, timestamp); `endif end else begin @@ -132,7 +132,7 @@ module VX_scope #( recording <= 1; delta <= 0; start_time <= timestamp; - `ifdef DBG_PRINT_SCOPE + `ifdef DBG_TRACE_SCOPE dpi_trace("%d: *** scope: recording start - start_time=%0d\n", $time, timestamp); `endif end @@ -161,7 +161,7 @@ module VX_scope #( if (stop || (waddr >= waddr_end)) begin - `ifdef DBG_PRINT_SCOPE + `ifdef DBG_TRACE_SCOPE dpi_trace("%d: *** scope: recording stop - waddr=(%0d, %0d)\n", $time, waddr, waddr_end); `endif waddr <= waddr; // keep last address @@ -229,7 +229,7 @@ module VX_scope #( assign bus_out = bus_out_r; -`ifdef DBG_PRINT_SCOPE +`ifdef DBG_TRACE_SCOPE always @(posedge clk) begin if (bus_read) begin dpi_trace("%d: scope-read: cmd=%0d, addr=%0d, value=%0h\n", $time, get_cmd, raddr, bus_out); diff --git a/hw/rtl/tex_unit/VX_tex_addr.sv b/hw/rtl/tex_unit/VX_tex_addr.sv index 40ef87a6..26a20566 100644 --- a/hw/rtl/tex_unit/VX_tex_addr.sv +++ b/hw/rtl/tex_unit/VX_tex_addr.sv @@ -150,7 +150,7 @@ module VX_tex_addr #( assign req_ready = ~stall_out; -`ifdef DBG_PRINT_TEX +`ifdef DBG_TRACE_TEX wire [`NW_BITS-1:0] rsp_wid; wire [31:0] rsp_PC; @@ -158,10 +158,10 @@ module VX_tex_addr #( always @(posedge clk) begin if (rsp_valid && rsp_ready) begin - $write("%t: core%0d-tex-addr: wid=%0d, PC=%0h, tmask=%b, req_filter=%0d, tride=%0d, addr=", + dpi_trace("%d: core%0d-tex-addr: wid=%0d, PC=%0h, tmask=%b, req_filter=%0d, tride=%0d, addr=", $time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask, rsp_filter, rsp_stride); - `PRINT_ARRAY2D(rsp_addr, 4, NUM_REQS); - $write("\n"); + `TRACE_ARRAY2D(rsp_addr, 4, NUM_REQS); + dpi_trace("\n"); end end `endif diff --git a/hw/rtl/tex_unit/VX_tex_mem.sv b/hw/rtl/tex_unit/VX_tex_mem.sv index 1dbfbcf1..059f01e6 100644 --- a/hw/rtl/tex_unit/VX_tex_mem.sv +++ b/hw/rtl/tex_unit/VX_tex_mem.sv @@ -257,7 +257,7 @@ module VX_tex_mem #( // Can accept new cache response? assign dcache_rsp_if.ready = ~(is_last_rsp && stall_out); -`ifdef DBG_PRINT_TEX +`ifdef DBG_TRACE_TEX wire [`NW_BITS-1:0] q_req_wid, req_wid, rsp_wid; wire [31:0] q_req_PC, req_PC, rsp_PC; assign {q_req_wid, q_req_PC} = q_req_info[`NW_BITS+32-1:0]; @@ -266,28 +266,28 @@ module VX_tex_mem #( always @(posedge clk) begin if (dcache_req_fire_any) begin - $write("%t: core%0d-tex-cache-req: wid=%0d, PC=%0h, tmask=%b, tag=%0h, addr=", + dpi_trace("%d: core%0d-tex-cache-req: wid=%0d, PC=%0h, tmask=%b, tag=%0h, addr=", $time, CORE_ID, q_req_wid, q_req_PC, dcache_req_fire, req_texel_idx); - `PRINT_ARRAY1D(req_texel_addr, NUM_REQS); - $write(", is_dup=%b\n", req_texel_dup); + `TRACE_ARRAY1D(req_texel_addr, NUM_REQS); + dpi_trace(", is_dup=%b\n", req_texel_dup); end if (dcache_rsp_fire) begin - $write("%t: core%0d-tex-cache-rsp: wid=%0d, PC=%0h, tmask=%b, tag=%0h, data=", + dpi_trace("%d: core%0d-tex-cache-rsp: wid=%0d, PC=%0h, tmask=%b, tag=%0h, data=", $time, CORE_ID, q_req_wid, q_req_PC, dcache_rsp_if.tmask, rsp_texel_idx); - `PRINT_ARRAY1D(dcache_rsp_if.data, NUM_REQS); - $write("\n"); + `TRACE_ARRAY1D(dcache_rsp_if.data, NUM_REQS); + dpi_trace("\n"); end if (req_valid && req_ready) begin - $write("%t: core%0d-tex-mem-req: wid=%0d, PC=%0h, tmask=%b, filter=%0d, stride=%0d, addr=", + dpi_trace("%d: core%0d-tex-mem-req: wid=%0d, PC=%0h, tmask=%b, filter=%0d, stride=%0d, addr=", $time, CORE_ID, req_wid, req_PC, req_tmask, req_filter, req_stride); - `PRINT_ARRAY2D(req_addr, 4, NUM_REQS); - $write("\n"); + `TRACE_ARRAY2D(req_addr, 4, NUM_REQS); + dpi_trace("\n"); end if (rsp_valid && rsp_ready) begin - $write("%t: core%0d-tex-mem-rsp: wid=%0d, PC=%0h, tmask=%b, data=", + dpi_trace("%d: core%0d-tex-mem-rsp: wid=%0d, PC=%0h, tmask=%b, data=", $time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask); - `PRINT_ARRAY2D(rsp_data, 4, NUM_REQS); - $write("\n"); + `TRACE_ARRAY2D(rsp_data, 4, NUM_REQS); + dpi_trace("\n"); end end `endif diff --git a/hw/rtl/tex_unit/VX_tex_sampler.sv b/hw/rtl/tex_unit/VX_tex_sampler.sv index a8bf7fc0..ac0f1496 100644 --- a/hw/rtl/tex_unit/VX_tex_sampler.sv +++ b/hw/rtl/tex_unit/VX_tex_sampler.sv @@ -116,7 +116,7 @@ module VX_tex_sampler #( // can accept new request? assign req_ready = ~stall_out; -`ifdef DBG_PRINT_TEX +`ifdef DBG_TRACE_TEX wire [`NW_BITS-1:0] req_wid, rsp_wid; wire [31:0] req_PC, rsp_PC; @@ -125,20 +125,20 @@ module VX_tex_sampler #( always @(posedge clk) begin if (req_valid && req_ready) begin - $write("%t: core%0d-tex-sampler-req: wid=%0d, PC=%0h, tmask=%b, format=%0d, data=", + dpi_trace("%d: core%0d-tex-sampler-req: wid=%0d, PC=%0h, tmask=%b, format=%0d, data=", $time, CORE_ID, req_wid, req_PC, req_tmask, req_format); - `PRINT_ARRAY2D(req_data, 4, NUM_REQS); - $write(", u0="); - `PRINT_ARRAY1D(req_blends[0], NUM_REQS); - $write(", v0="); - `PRINT_ARRAY1D(req_blends[1], NUM_REQS); - $write("\n"); + `TRACE_ARRAY2D(req_data, 4, NUM_REQS); + dpi_trace(", u0="); + `TRACE_ARRAY1D(req_blends[0], NUM_REQS); + dpi_trace(", v0="); + `TRACE_ARRAY1D(req_blends[1], NUM_REQS); + dpi_trace("\n"); end if (rsp_valid && rsp_ready) begin - $write("%t: core%0d-tex-sampler-rsp: wid=%0d, PC=%0h, tmask=%b, data=", + dpi_trace("%d: core%0d-tex-sampler-rsp: wid=%0d, PC=%0h, tmask=%b, data=", $time, CORE_ID, rsp_wid, rsp_PC, rsp_tmask); - `PRINT_ARRAY1D(rsp_data, NUM_REQS); - $write("\n"); + `TRACE_ARRAY1D(rsp_data, NUM_REQS); + dpi_trace("\n"); end end `endif diff --git a/hw/rtl/tex_unit/VX_tex_unit.sv b/hw/rtl/tex_unit/VX_tex_unit.sv index 66afd301..6be6aa43 100644 --- a/hw/rtl/tex_unit/VX_tex_unit.sv +++ b/hw/rtl/tex_unit/VX_tex_unit.sv @@ -199,34 +199,34 @@ module VX_tex_unit #( .rsp_ready (tex_rsp_if.ready) ); -`ifdef DBG_PRINT_TEX +`ifdef DBG_TRACE_TEX always @(posedge clk) begin if (tex_req_if.valid && tex_req_if.ready) begin for (integer i = 0; i < `NUM_TEX_UNITS; ++i) begin if (csrs_dirty[i]) begin - $display("%t: core%0d-tex-csr: tex%0d_addr=%0h", $time, CORE_ID, i, tex_baddr[i]); - $display("%t: core%0d-tex-csr: tex%0d_format=%0h", $time, CORE_ID, i, tex_format[i]); - $display("%t: core%0d-tex-csr: tex%0d_wrap_u=%0h", $time, CORE_ID, i, tex_wraps[i][0]); - $display("%t: core%0d-tex-csr: tex%0d_wrap_v=%0h", $time, CORE_ID, i, tex_wraps[i][1]); - $display("%t: core%0d-tex-csr: tex%0d_filter=%0h", $time, CORE_ID, i, tex_filter[i]); - $display("%t: core%0d-tex-csr: tex%0d_mipoff[0]=%0h", $time, CORE_ID, i, tex_mipoff[i][0]); - $display("%t: core%0d-tex-csr: tex%0d_width[0]=%0h", $time, CORE_ID, i, tex_dims[i][0][0]); - $display("%t: core%0d-tex-csr: tex%0d_height[0]=%0h", $time, CORE_ID, i, tex_dims[i][0][1]); + dpi_trace("%d: core%0d-tex-csr: tex%0d_addr=%0h\n", $time, CORE_ID, i, tex_baddr[i]); + dpi_trace("%d: core%0d-tex-csr: tex%0d_format=%0h\n", $time, CORE_ID, i, tex_format[i]); + dpi_trace("%d: core%0d-tex-csr: tex%0d_wrap_u=%0h\n", $time, CORE_ID, i, tex_wraps[i][0]); + dpi_trace("%d: core%0d-tex-csr: tex%0d_wrap_v=%0h\n", $time, CORE_ID, i, tex_wraps[i][1]); + dpi_trace("%d: core%0d-tex-csr: tex%0d_filter=%0h\n", $time, CORE_ID, i, tex_filter[i]); + dpi_trace("%d: core%0d-tex-csr: tex%0d_mipoff[0]=%0h\n", $time, CORE_ID, i, tex_mipoff[i][0]); + dpi_trace("%d: core%0d-tex-csr: tex%0d_width[0]=%0h\n", $time, CORE_ID, i, tex_dims[i][0][0]); + dpi_trace("%d: core%0d-tex-csr: tex%0d_height[0]=%0h\n", $time, CORE_ID, i, tex_dims[i][0][1]); end end - $write("%t: core%0d-tex-req: wid=%0d, PC=%0h, tmask=%b, unit=%0d, lod=%0h, u=", + dpi_trace("%d: core%0d-tex-req: wid=%0d, PC=%0h, tmask=%b, unit=%0d, lod=%0h, u=", $time, CORE_ID, tex_req_if.wid, tex_req_if.PC, tex_req_if.tmask, tex_req_if.unit, tex_req_if.lod); - `PRINT_ARRAY1D(tex_req_if.coords[0], `NUM_THREADS); - $write(", v="); - `PRINT_ARRAY1D(tex_req_if.coords[1], `NUM_THREADS); - $write("\n"); + `TRACE_ARRAY1D(tex_req_if.coords[0], `NUM_THREADS); + dpi_trace(", v="); + `TRACE_ARRAY1D(tex_req_if.coords[1], `NUM_THREADS); + dpi_trace("\n"); end if (tex_rsp_if.valid && tex_rsp_if.ready) begin - $write("%t: core%0d-tex-rsp: wid=%0d, PC=%0h, tmask=%b, data=", + dpi_trace("%d: core%0d-tex-rsp: wid=%0d, PC=%0h, tmask=%b, data=", $time, CORE_ID, tex_rsp_if.wid, tex_rsp_if.PC, tex_rsp_if.tmask); - `PRINT_ARRAY1D(tex_rsp_if.data, `NUM_THREADS); - $write("\n"); + `TRACE_ARRAY1D(tex_rsp_if.data, `NUM_THREADS); + dpi_trace("\n"); end end `endif diff --git a/hw/syn/opae/Makefile b/hw/syn/opae/Makefile index 7c1ab010..010baea3 100644 --- a/hw/syn/opae/Makefile +++ b/hw/syn/opae/Makefile @@ -8,21 +8,21 @@ else RUN_SYNTH=qsub-synth endif -# control RTL debug print states -DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA -DBG_PRINT_FLAGS += -DDBG_PRINT_MEM -DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE -DBG_PRINT_FLAGS += -DDBG_PRINT_AVS -DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE -DBG_PRINT_FLAGS += -DDBG_PRINT_TEX +# control RTL debug tracing states +DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA +DBG_TRACE_FLAGS += -DDBG_TRACE_MEM +DBG_TRACE_FLAGS += -DDBG_TRACE_OPAE +DBG_TRACE_FLAGS += -DDBG_TRACE_AVS +DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE +DBG_TRACE_FLAGS += -DDBG_TRACE_TEX -DBG_FLAGS += $(DBG_PRINT_FLAGS) +DBG_FLAGS += $(DBG_TRACE_FLAGS) DBG_FLAGS += -DDBG_CACHE_REQ_INFO CONFIG1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 -DL2_ENABLE=0 -DL3_ENABLE=0 $(CONFIGS) diff --git a/hw/unit_tests/cache/Makefile b/hw/unit_tests/cache/Makefile index b2211887..96c2e9f1 100644 --- a/hw/unit_tests/cache/Makefile +++ b/hw/unit_tests/cache/Makefile @@ -1,18 +1,18 @@ PARAMS += -DCACHE_SIZE=4096 -DCACHE_WORD_SIZE=4 -DCACHE_LINE_SIZE=16 -DCACHE_NUM_BANKS=4 -DCACHE_CREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 -# control RTL debug print states -DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ - -DDBG_PRINT_CORE_DCACHE \ - -DDBG_PRINT_CACHE_BANK \ - -DDBG_PRINT_CACHE_SNP \ - -DDBG_PRINT_CACHE_MSHR \ - -DDBG_PRINT_CACHE_TAG \ - -DDBG_PRINT_CACHE_DATA \ - -DDBG_PRINT_MEM \ - -DDBG_PRINT_OPAE \ - -DDBG_PRINT_AVS +# control RTL debug tracing states +DBG_TRACE_FLAGS = -DDBG_TRACE_CORE_ICACHE \ + -DDBG_TRACE_CORE_DCACHE \ + -DDBG_TRACE_CACHE_BANK \ + -DDBG_TRACE_CACHE_SNP \ + -DDBG_TRACE_CACHE_MSHR \ + -DDBG_TRACE_CACHE_TAG \ + -DDBG_TRACE_CACHE_DATA \ + -DDBG_TRACE_MEM \ + -DDBG_TRACE_OPAE \ + -DDBG_TRACE_AVS -#DBG_PRINT=$(DBG_PRINT_FLAGS) +#DBG_PRINT=$(DBG_TRACE_FLAGS) INCLUDE = -I../../rtl/ -I../../rtl/cache -I../../rtl/libs diff --git a/sim/rtlsim/Makefile b/sim/rtlsim/Makefile index 6f82e73a..a0c8d339 100644 --- a/sim/rtlsim/Makefile +++ b/sim/rtlsim/Makefile @@ -8,21 +8,21 @@ CXXFLAGS += -I../../common/softfloat/source/include LDFLAGS += ../../common/softfloat/build/Linux-x86_64-GCC/softfloat.a -# control RTL debug print states -DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA -DBG_PRINT_FLAGS += -DDBG_PRINT_MEM -DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE -DBG_PRINT_FLAGS += -DDBG_PRINT_AVS -DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE -DBG_PRINT_FLAGS += -DDBG_PRINT_TEX +# control RTL debug tracing states +DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA +DBG_TRACE_FLAGS += -DDBG_TRACE_MEM +DBG_TRACE_FLAGS += -DDBG_TRACE_OPAE +DBG_TRACE_FLAGS += -DDBG_TRACE_AVS +DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE +DBG_TRACE_FLAGS += -DDBG_TRACE_TEX -DBG_FLAGS += $(DBG_PRINT_FLAGS) +DBG_FLAGS += $(DBG_TRACE_FLAGS) DBG_FLAGS += -DDBG_CACHE_REQ_INFO DBG_FLAGS += -DVCD_OUTPUT diff --git a/sim/vlsim/Makefile b/sim/vlsim/Makefile index 9b6fa274..d956f2fa 100644 --- a/sim/vlsim/Makefile +++ b/sim/vlsim/Makefile @@ -9,21 +9,21 @@ CXXFLAGS += -I../../common/softfloat/source/include LDFLAGS += -shared ../../common/softfloat/build/Linux-x86_64-GCC/softfloat.a -# control RTL debug print states -DBG_PRINT_FLAGS += -DDBG_PRINT_PIPELINE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_ICACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CORE_DCACHE -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_BANK -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_MSHR -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_TAG -DBG_PRINT_FLAGS += -DDBG_PRINT_CACHE_DATA -DBG_PRINT_FLAGS += -DDBG_PRINT_MEM -DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE -DBG_PRINT_FLAGS += -DDBG_PRINT_AVS -DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE -DBG_PRINT_FLAGS += -DDBG_PRINT_TEX +# control RTL debug tracing states +DBG_TRACE_FLAGS += -DDBG_TRACE_PIPELINE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_DCACHE +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_BANK +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_MSHR +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_TAG +DBG_TRACE_FLAGS += -DDBG_TRACE_CACHE_DATA +DBG_TRACE_FLAGS += -DDBG_TRACE_MEM +DBG_TRACE_FLAGS += -DDBG_TRACE_OPAE +DBG_TRACE_FLAGS += -DDBG_TRACE_AVS +DBG_TRACE_FLAGS += -DDBG_TRACE_SCOPE +DBG_TRACE_FLAGS += -DDBG_TRACE_TEX -DBG_FLAGS += $(DBG_PRINT_FLAGS) +DBG_FLAGS += $(DBG_TRACE_FLAGS) DBG_FLAGS += -DDBG_CACHE_REQ_INFO SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp