Before FE BE abstraction
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@@ -3,14 +3,13 @@
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module VX_execute (
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VX_frE_to_bckE_req_inter VX_bckE_req,
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VX_forward_exe_inter VX_fwd_exe,
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input wire[31:0] in_csr_data,
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VX_mem_req_inter VX_exe_mem_req,
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output wire[11:0] out_csr_address,
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output wire out_is_csr,
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output reg[31:0] out_csr_result,
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output wire[`NT_M1:0][31:0] out_a_reg_data,
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output wire[`NT_M1:0][31:0] out_b_reg_data,
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output wire out_jal,
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output wire[31:0] out_jal_dest,
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output wire out_branch_stall
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@@ -81,13 +80,6 @@ module VX_execute (
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assign out_branch_stall = ((in_branch_type != `NO_BRANCH) || in_jal ) ? `STALL : `NO_STALL;
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genvar ind;
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for (ind = 0; ind <= `NT_M1; ind = ind + 1) begin
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assign out_a_reg_data[ind] = in_a_reg_data[ind];
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assign out_b_reg_data[ind] = in_b_reg_data[ind];
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end
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assign VX_exe_mem_req.mem_read = VX_bckE_req.mem_read;
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assign VX_exe_mem_req.mem_write = VX_bckE_req.mem_write;
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assign VX_exe_mem_req.wb = VX_bckE_req.wb;
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@@ -104,6 +96,13 @@ module VX_execute (
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assign VX_exe_mem_req.warp_num = VX_bckE_req.warp_num;
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assign VX_fwd_exe.dest = VX_exe_mem_req.rd;
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assign VX_fwd_exe.wb = VX_exe_mem_req.wb;
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assign VX_fwd_exe.alu_result = VX_exe_mem_req.alu_result;
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assign VX_fwd_exe.PC_next = VX_exe_mem_req.PC_next;
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assign VX_fwd_exe.warp_num = VX_exe_mem_req.warp_num;
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assign out_is_csr = VX_bckE_req.is_csr;
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assign out_csr_address = VX_bckE_req.csr_address;
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