minor update
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@@ -1,7 +1,7 @@
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#CFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors
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CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
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CFLAGS += -I../../include -I../../../hw/simulate -I../../../runtime
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CFLAGS += -I../../include -I../../../hw/simulate -I../../../hw
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# control RTL debug print states
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DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
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@@ -19,7 +19,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
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MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
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#DEBUG = 1
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AFU=1
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#AFU=1
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CFLAGS += -fPIC
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@@ -7,6 +7,7 @@
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#include <chrono>
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#include <vortex.h>
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#include <ram.h>
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#include <simulator.h>
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///////////////////////////////////////////////////////////////////////////////
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@@ -59,6 +60,7 @@ class vx_device {
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public:
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vx_device() {
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mem_allocation_ = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR);
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simulator_.attach_ram(&ram_);
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}
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~vx_device() {
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@@ -144,6 +146,7 @@ public:
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private:
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size_t mem_allocation_;
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RAM ram_;
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Simulator simulator_;
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std::future<void> future_;
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};
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@@ -436,7 +436,7 @@ begin
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end
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if (cci_dram_wr_req_fire) begin
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cci_dram_wr_req_addr <= cci_dram_wr_req_addr + ((t_cci_rdq_tag'(cci_dram_wr_req_ctr) == (DRAM_ADDR_WIDTH)'(CCI_RD_WINDOW_SIZE-1)) ? (DRAM_ADDR_WIDTH)'(CCI_RD_WINDOW_SIZE) : 0);
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cci_dram_wr_req_addr <= cci_dram_wr_req_addr + ((t_cci_rdq_tag'(cci_dram_wr_req_ctr) == t_cci_rdq_tag'(CCI_RD_WINDOW_SIZE-1)) ? (DRAM_ADDR_WIDTH)'(CCI_RD_WINDOW_SIZE) : 0);
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cci_dram_wr_req_ctr <= cci_dram_wr_req_ctr + 1;
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`ifdef DBG_PRINT_OPAE
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$display("%t: AVS Wr Req: addr=%0h, data=%0h, rem=%0d", $time, `DRAM_TO_BYTE_ADDR(avs_address), avs_writedata, (cci_dram_wr_req_ctr + 1));
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@@ -121,7 +121,7 @@ module VX_generic_queue #(
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if (!reading) begin
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empty_r <= 0;
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if (size_r == SIZE-1) begin
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if (size_r == ($bits(size_r)'(SIZE-1))) begin
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full_r <= 1;
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end
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size_r <= size_r + 1;
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