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Made the cache module configurable for multi-instantiation

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This commit is contained in:
felsabbagh3
2020-03-07 00:49:40 -08:00
parent fb23812e95
commit 9bf0add937
22 changed files with 1209 additions and 493 deletions
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68
rtl/VX_cache/VX_cache_dram_req_arb.v
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@@ -1,21 +1,65 @@
`include "VX_cache_config.v"
module VX_cache_dram_req_arb (
module VX_cache_dram_req_arb
#(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUMBER_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUMBER_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
)
(
input wire clk,
input wire reset,
// Fill Request
output wire dfqq_full,
input wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req,
input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr,
input wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req,
input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr,
// DFQ Request
output wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop,
input wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req,
input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr,
input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data,
input wire[`NUMBER_BANKS-1:0] per_bank_dram_because_of_snp,
output wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop,
input wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req,
input wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr,
input wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data,
input wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp,
// real Dram request
output wire dram_req,
@@ -48,9 +92,9 @@ module VX_cache_dram_req_arb (
.dfqq_full (dfqq_full)
);
wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank;
wire[`NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp;
VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb(
wire[`vx_clog2(NUMBER_BANKS)-1:0] dwb_bank;
wire[NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp;
VX_generic_priority_encoder #(.N(NUMBER_BANKS)) VX_sel_dwb(
.valids(use_wb_valid),
.index (dwb_bank),
.found (dwb_valid)
@@ -64,7 +108,7 @@ module VX_cache_dram_req_arb (
assign dram_req_write = dwb_valid;
assign dram_req_read = dfqq_req && !dwb_valid;
assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK;
assign dram_req_size = `BANK_LINE_SIZE_BYTES;
assign dram_req_size = BANK_LINE_SIZE_BYTES;
assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;
assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0;