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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-19 03:38:00 -04:00
parent 460aabf6b1
commit 9b476f1e17
97 changed files with 3127 additions and 18563 deletions
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9
hw/rtl/interfaces/VX_branch_response_inter.v
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@@ -4,10 +4,11 @@
`include "../VX_define.vh"
interface VX_branch_response_inter ();
wire valid_branch;
wire branch_dir;
wire[31:0] branch_dest;
wire[`NW_BITS-1:0] branch_warp_num;
wire valid_branch;
wire branch_dir;
wire [31:0] branch_dest;
wire [`NW_BITS-1:0] branch_warp_num;
endinterface

18
hw/rtl/interfaces/VX_csr_req_inter.v
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@@ -5,15 +5,15 @@
interface VX_csr_req_inter ();
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire[4:0] rd;
wire[1:0] wb;
wire[4:0] alu_op;
wire is_csr;
wire[11:0] csr_address;
wire csr_immed;
wire[31:0] csr_mask;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [4:0] alu_op;
wire is_csr;
wire [11:0] csr_address;
wire csr_immed;
wire [31:0] csr_mask;
endinterface

10
hw/rtl/interfaces/VX_csr_wb_inter.v
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@@ -5,12 +5,12 @@
interface VX_csr_wb_inter ();
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire[4:0] rd;
wire[1:0] wb;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire[`NUM_THREADS-1:0][31:0] csr_result;
wire [`NUM_THREADS-1:0][31:0] csr_result;
endinterface

10
hw/rtl/interfaces/VX_dcache_request_inter.v
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@@ -5,11 +5,11 @@
interface VX_dcache_request_inter ();
wire[`NUM_THREADS-1:0][31:0] out_cache_driver_in_address;
wire[2:0] out_cache_driver_in_mem_read;
wire[2:0] out_cache_driver_in_mem_write;
wire[`NUM_THREADS-1:0] out_cache_driver_in_valid;
wire[`NUM_THREADS-1:0][31:0] out_cache_driver_in_data;
wire [`NUM_THREADS-1:0][31:0] out_cache_driver_in_address;
wire [2:0] out_cache_driver_in_mem_read;
wire [2:0] out_cache_driver_in_mem_write;
wire [`NUM_THREADS-1:0] out_cache_driver_in_valid;
wire [`NUM_THREADS-1:0][31:0] out_cache_driver_in_data;
endinterface

4
hw/rtl/interfaces/VX_dcache_response_inter.v
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@@ -5,8 +5,8 @@
interface VX_dcache_response_inter ();
wire[`NUM_THREADS-1:0][31:0] in_cache_driver_out_data;
wire delay;
wire [`NUM_THREADS-1:0][31:0] in_cache_driver_out_data;
wire delay;
endinterface

17
hw/rtl/interfaces/VX_dram_req_rsp_inter.v
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@@ -6,18 +6,19 @@
interface VX_dram_req_rsp_inter #(
parameter NUM_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4) ();
parameter NUM_WORDS_PER_BLOCK = 4
) ();
// Req
wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr;
wire o_m_valid;
wire[NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write;
wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr;
wire o_m_valid;
wire [NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write;
// Rsp
wire[NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;
wire [NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;
endinterface

52
hw/rtl/interfaces/VX_exec_unit_req_inter.v
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@@ -6,43 +6,43 @@
interface VX_exec_unit_req_inter ();
// Meta
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire[31:0] curr_PC;
wire[31:0] PC_next;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [31:0] curr_PC;
wire [31:0] PC_next;
// Write Back Info
wire[4:0] rd;
wire[1:0] wb;
wire [4:0] rd;
wire [1:0] wb;
// Data and alu op
wire[`NUM_THREADS-1:0][31:0] a_reg_data;
wire[`NUM_THREADS-1:0][31:0] b_reg_data;
wire[4:0] alu_op;
wire[4:0] rs1;
wire[4:0] rs2;
wire rs2_src;
wire[31:0] itype_immed;
wire[19:0] upper_immed;
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [`NUM_THREADS-1:0][31:0] b_reg_data;
wire [4:0] alu_op;
wire [4:0] rs1;
wire [4:0] rs2;
wire rs2_src;
wire [31:0] itype_immed;
wire [19:0] upper_immed;
// Branch type
wire[2:0] branch_type;
wire [2:0] branch_type;
// Jal info
wire jalQual;
wire jal;
wire[31:0] jal_offset;
wire jalQual;
wire jal;
wire [31:0] jal_offset;
/* verilator lint_off UNUSED */
wire ebreak;
wire wspawn;
/* verilator lint_on UNUSED */
/* verilator lint_off UNUSED */
wire ebreak;
wire wspawn;
/* verilator lint_on UNUSED */
// CSR info
wire is_csr;
wire[11:0] csr_address;
wire csr_immed;
wire[31:0] csr_mask;
wire is_csr;
wire [11:0] csr_address;
wire csr_immed;
wire [31:0] csr_mask;
endinterface

58
hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v
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@@ -5,37 +5,37 @@
interface VX_frE_to_bckE_req_inter ();
wire[11:0] csr_address;
wire is_csr;
wire csr_immed;
wire[31:0] csr_mask;
wire[4:0] rd;
wire[4:0] rs1;
wire[4:0] rs2;
wire[4:0] alu_op;
wire[1:0] wb;
wire rs2_src;
wire[31:0] itype_immed;
wire[2:0] mem_read;
wire[2:0] mem_write;
wire[2:0] branch_type;
wire[19:0] upper_immed;
wire[31:0] curr_PC;
/* verilator lint_off UNUSED */
wire ebreak;
/* verilator lint_on UNUSED */
wire jalQual;
wire jal;
wire[31:0] jal_offset;
wire[31:0] PC_next;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire [11:0] csr_address;
wire is_csr;
wire csr_immed;
wire [31:0] csr_mask;
wire [4:0] rd;
wire [4:0] rs1;
wire [4:0] rs2;
wire [4:0] alu_op;
wire [1:0] wb;
wire rs2_src;
wire [31:0] itype_immed;
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [2:0] branch_type;
wire [19:0] upper_immed;
wire [31:0] curr_PC;
/* verilator lint_off UNUSED */
wire ebreak;
/* verilator lint_on UNUSED */
wire jalQual;
wire jal;
wire [31:0] jal_offset;
wire [31:0] PC_next;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
// GPGPU stuff
wire is_wspawn;
wire is_tmc;
wire is_split;
wire is_barrier;
wire is_wspawn;
wire is_tmc;
wire is_split;
wire is_barrier;
endinterface

6
hw/rtl/interfaces/VX_gpr_clone_inter.v
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@@ -5,12 +5,10 @@
`include "../VX_define.vh"
interface VX_gpr_clone_inter ();
/* verilator lint_off UNUSED */
wire is_clone;
wire[`NW_BITS-1:0] warp_num;
wire is_clone;
wire[`NW_BITS-1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface
`endif

4
hw/rtl/interfaces/VX_gpr_data_inter.v
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@@ -6,8 +6,8 @@
interface VX_gpr_data_inter ();
wire[`NUM_THREADS-1:0][31:0] a_reg_data;
wire[`NUM_THREADS-1:0][31:0] b_reg_data;
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [`NUM_THREADS-1:0][31:0] b_reg_data;
endinterface

6
hw/rtl/interfaces/VX_gpr_read_inter.v
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@@ -5,9 +5,9 @@
interface VX_gpr_read_inter ();
wire[4:0] rs1;
wire[4:0] rs2;
wire[`NW_BITS-1:0] warp_num;
wire [4:0] rs1;
wire [4:0] rs2;
wire [`NW_BITS-1:0] warp_num;
endinterface

3
hw/rtl/interfaces/VX_gpr_wspawn_inter.v
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@@ -6,10 +6,9 @@
interface VX_gpr_wspawn_inter ();
/* verilator lint_off UNUSED */
wire is_wspawn;
wire[`NW_BITS-1:0] which_wspawn;
wire [`NW_BITS-1:0] which_wspawn;
// wire[`NW_BITS-1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface
`endif

25
hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v
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@@ -1,33 +1,20 @@
`ifndef VX_GPU_DRAM_DCACHE_REQ
`define VX_GPU_DRAM_DCACHE_REQ
`include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_req_inter
#(
parameter BANK_LINE_WORDS = 2
)
();
interface VX_gpu_dcache_dram_req_inter #(
parameter BANK_LINE_WORDS = 2
) ();
// DRAM Request
wire dram_req;
wire dram_req_write;
wire dram_req_read;
wire [31:0] dram_req_addr;
wire [31:0] dram_req_size;
wire [BANK_LINE_WORDS-1:0][31:0] dram_req_data;
wire [BANK_LINE_WORDS-1:0][31:0] dram_req_data;
wire dram_req_full;
// Snoop
wire dram_because_of_snp;
wire dram_snp_full;
// DRAM Cache can't accept response
wire dram_fill_accept;
// DRAM Cache can't accept request
wire dram_req_delay;
wire dram_rsp_ready;
endinterface

18
hw/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v
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@@ -1,18 +0,0 @@
`ifndef VX_GPU_DRAM_DCACHE_RES
`define VX_GPU_DRAM_DCACHE_RES
`include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_res_inter
#(
parameter BANK_LINE_WORDS = 2
)
();
// DRAM Rsponse
wire dram_fill_rsp;
wire [31:0] dram_fill_rsp_addr;
wire [BANK_LINE_WORDS-1:0][31:0] dram_fill_rsp_data;
endinterface
`endif

16
hw/rtl/interfaces/VX_gpu_dcache_dram_rsp_inter.v Normal file
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@@ -0,0 +1,16 @@
`ifndef VX_GPU_DRAM_DCACHE_RSP
`define VX_GPU_DRAM_DCACHE_RSP
`include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_rsp_inter #(
parameter BANK_LINE_WORDS = 2
) ();
// DRAM Response
wire dram_rsp_valid;
wire [31:0] dram_rsp_addr;
wire [BANK_LINE_WORDS-1:0][31:0] dram_rsp_data;
endinterface
`endif

10
hw/rtl/interfaces/VX_gpu_dcache_req_inter.v
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@@ -1,15 +1,11 @@
`ifndef VX_GPU_DCACHE_REQ
`define VX_GPU_DCACHE_REQ
`include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_req_inter
#(
parameter NUM_REQUESTS = 32
)
();
interface VX_gpu_dcache_req_inter #(
parameter NUM_REQUESTS = 32
) ();
// Core Request
wire [NUM_REQUESTS-1:0] core_req_valid;

13
hw/rtl/interfaces/VX_gpu_dcache_res_inter.v → hw/rtl/interfaces/VX_gpu_dcache_rsp_inter.v
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@@ -1,17 +1,18 @@
`ifndef VX_GPU_DCACHE_RES
`define VX_GPU_DCACHE_RES
`ifndef VX_GPU_DCACHE_RSP
`define VX_GPU_DCACHE_RSP
`include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_res_inter
#(
parameter NUM_REQUESTS = 32
) ();
interface VX_gpu_dcache_rsp_inter #(
parameter NUM_REQUESTS = 32
) ();
// Cache WB
wire [NUM_REQUESTS-1:0] core_wb_valid;
/* verilator lint_off UNUSED */
wire [4:0] core_wb_req_rd;
wire [1:0] core_wb_req_wb;
/* verilator lint_off UNUSED */
wire [`NW_BITS-1:0] core_wb_warp_num;
wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata;
wire [NUM_REQUESTS-1:0][31:0] core_wb_pc;

2
hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v
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@@ -5,7 +5,7 @@
interface VX_gpu_dcache_snp_req_inter ();
// Snoop Req
wire snp_req;
wire snp_req_valid;
wire [31:0] snp_req_addr;
endinterface

8
hw/rtl/interfaces/VX_gpu_inst_req_inter.v
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@@ -5,8 +5,8 @@
interface VX_gpu_inst_req_inter();
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire is_wspawn;
wire is_tmc;
wire is_split;
@@ -15,8 +15,8 @@ interface VX_gpu_inst_req_inter();
wire[31:0] pc_next;
wire[`NUM_THREADS-1:0][31:0] a_reg_data;
wire[31:0] rd2;
wire [`NUM_THREADS-1:0][31:0] a_reg_data;
wire [31:0] rd2;
endinterface

7
hw/rtl/interfaces/VX_gpu_snp_req_rsp.v
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@@ -6,11 +6,12 @@
interface VX_gpu_snp_req_rsp ();
// Snoop request
wire snp_req;
wire[31:0] snp_req_addr;
wire snp_req_valid;
wire [31:0] snp_req_addr;
wire snp_req_full;
// Snoop Response
wire snp_delay;
// TODO:
endinterface

10
hw/rtl/interfaces/VX_icache_request_inter.v
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@@ -6,11 +6,11 @@
interface VX_icache_request_inter ();
wire[31:0] pc_address;
wire[2:0] out_cache_driver_in_mem_read;
wire[2:0] out_cache_driver_in_mem_write;
wire out_cache_driver_in_valid;
wire[31:0] out_cache_driver_in_data;
wire [31:0] pc_address;
wire [2:0] out_cache_driver_in_mem_read;
wire [2:0] out_cache_driver_in_mem_write;
wire out_cache_driver_in_valid;
wire [31:0] out_cache_driver_in_data;
endinterface

4
hw/rtl/interfaces/VX_icache_response_inter.v
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@@ -7,8 +7,8 @@ interface VX_icache_response_inter ();
// wire ready;
// wire stall;
wire[31:0] instruction;
wire delay;
wire [31:0] instruction;
wire delay;
endinterface

12
hw/rtl/interfaces/VX_inst_exec_wb_inter.v
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@@ -6,12 +6,12 @@
interface VX_inst_exec_wb_inter ();
wire[`NUM_THREADS-1:0][31:0] alu_result;
wire[31:0] exec_wb_pc;
wire[4:0] rd;
wire[1:0] wb;
wire[`NUM_THREADS-1:0] wb_valid;
wire[`NW_BITS-1:0] wb_warp_num;
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [31:0] exec_wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
endinterface

12
hw/rtl/interfaces/VX_inst_mem_wb_inter.v
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@@ -6,12 +6,12 @@
interface VX_inst_mem_wb_inter ();
wire[`NUM_THREADS-1:0][31:0] loaded_data;
wire[31:0] mem_wb_pc;
wire[4:0] rd;
wire[1:0] wb;
wire[`NUM_THREADS-1:0] wb_valid;
wire[`NW_BITS-1:0] wb_warp_num;
wire [`NUM_THREADS-1:0][31:0] loaded_data;
wire [31:0] mem_wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
endinterface

8
hw/rtl/interfaces/VX_inst_meta_inter.v
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@@ -5,10 +5,10 @@
interface VX_inst_meta_inter ();
wire[31:0] instruction;
wire[31:0] inst_pc;
wire[`NW_BITS-1:0] warp_num;
wire[`NUM_THREADS-1:0] valid;
wire [31:0] instruction;
wire [31:0] inst_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0] valid;
endinterface

4
hw/rtl/interfaces/VX_jal_response_inter.v
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@@ -7,8 +7,8 @@
interface VX_jal_response_inter ();
wire jal;
wire[31:0] jal_dest;
wire[`NW_BITS-1:0] jal_warp_num;
wire [31:0] jal_dest;
wire [`NW_BITS-1:0] jal_warp_num;
endinterface

4
hw/rtl/interfaces/VX_join_inter.v
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@@ -6,8 +6,8 @@
interface VX_join_inter ();
wire is_join;
wire[`NW_BITS-1:0] join_warp_num;
wire is_join;
wire [`NW_BITS-1:0] join_warp_num;
endinterface

20
hw/rtl/interfaces/VX_lsu_req_inter.v
View File

@@ -6,16 +6,16 @@
interface VX_lsu_req_inter ();
wire[`NUM_THREADS-1:0] valid;
wire[31:0] lsu_pc;
wire[`NW_BITS-1:0] warp_num;
wire[`NUM_THREADS-1:0][31:0] store_data;
wire[`NUM_THREADS-1:0][31:0] base_address; // A reg data
wire[31:0] offset; // itype_immed
wire[2:0] mem_read;
wire[2:0] mem_write;
wire[4:0] rd;
wire[1:0] wb;
wire [`NUM_THREADS-1:0] valid;
wire [31:0] lsu_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data
wire [31:0] offset; // itype_immed
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [4:0] rd;
wire [1:0] wb;
endinterface

28
hw/rtl/interfaces/VX_mem_req_inter.v
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@@ -5,20 +5,20 @@
interface VX_mem_req_inter ();
wire[`NUM_THREADS-1:0][31:0] alu_result;
wire[2:0] mem_read;
wire[2:0] mem_write;
wire[4:0] rd;
wire[1:0] wb;
wire[4:0] rs1;
wire[4:0] rs2;
wire[`NUM_THREADS-1:0][31:0] rd2;
wire[31:0] PC_next;
wire[31:0] curr_PC;
wire[31:0] branch_offset;
wire[2:0] branch_type;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [4:0] rd;
wire [1:0] wb;
wire [4:0] rs1;
wire [4:0] rs2;
wire [`NUM_THREADS-1:0][31:0] rd2;
wire [31:0] PC_next;
wire [31:0] curr_PC;
wire [31:0] branch_offset;
wire [2:0] branch_type;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
endinterface

14
hw/rtl/interfaces/VX_mw_wb_inter.v
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@@ -6,13 +6,13 @@
interface VX_mw_wb_inter ();
wire[`NUM_THREADS-1:0][31:0] alu_result;
wire[`NUM_THREADS-1:0][31:0] mem_result;
wire[4:0] rd;
wire[1:0] wb;
wire[31:0] PC_next;
wire[`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [`NUM_THREADS-1:0][31:0] mem_result;
wire [4:0] rd;
wire [1:0] wb;
wire [31:0] PC_next;
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
endinterface

34
hw/rtl/interfaces/VX_warp_ctl_inter.v
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@@ -6,27 +6,29 @@
interface VX_warp_ctl_inter ();
wire[`NW_BITS-1:0] warp_num;
wire change_mask;
wire[`NUM_THREADS-1:0] thread_mask;
wire [`NW_BITS-1:0] warp_num;
wire change_mask;
wire [`NUM_THREADS-1:0] thread_mask;
wire wspawn;
wire[31:0] wspawn_pc;
wire[`NUM_WARPS-1:0] wspawn_new_active;
wire wspawn;
wire [31:0] wspawn_pc;
wire [`NUM_WARPS-1:0] wspawn_new_active;
wire ebreak;
wire ebreak;
// barrier
wire is_barrier;
wire[31:0] barrier_id;
wire[$clog2(`NUM_WARPS):0] num_warps;
wire is_barrier;
wire [31:0] barrier_id;
wire [$clog2(`NUM_WARPS):0] num_warps;
wire is_split;
wire dont_split;
wire[`NW_BITS-1:0] split_warp_num;
wire[`NUM_THREADS-1:0] split_new_mask;
wire[`NUM_THREADS-1:0] split_later_mask;
wire[31:0] split_save_pc;
wire is_split;
wire dont_split;
/* verilator lint_off UNUSED */
wire [`NW_BITS-1:0] split_warp_num;
/* verilator lint_on UNUSED */
wire [`NUM_THREADS-1:0] split_new_mask;
wire [`NUM_THREADS-1:0] split_later_mask;
wire [31:0] split_save_pc;
endinterface

12
hw/rtl/interfaces/VX_wb_inter.v
View File

@@ -5,12 +5,12 @@
interface VX_wb_inter ();
wire[`NUM_THREADS-1:0][31:0] write_data;
wire[31:0] wb_pc;
wire[4:0] rd;
wire[1:0] wb;
wire[`NUM_THREADS-1:0] wb_valid;
wire[`NW_BITS-1:0] wb_warp_num;
wire [`NUM_THREADS-1:0][31:0] write_data;
wire [31:0] wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
endinterface

4
hw/rtl/interfaces/VX_wstall_inter.v
View File

@@ -5,8 +5,8 @@
interface VX_wstall_inter();
wire wstall;
wire[`NW_BITS-1:0] warp_num;
wire wstall;
wire [`NW_BITS-1:0] warp_num;
endinterface