minor update

2021-01-01 20:24:18 -08:00
parent da9649c2a3
commit 93c36273fa
5 changed files with 45 additions and 72 deletions
--- a/hw/rtl/cache/VX_miss_resrv.v
+++ b/hw/rtl/cache/VX_miss_resrv.v
@@ -53,7 +53,7 @@ module VX_miss_resrv #(
    // dequeue
    input wire                          dequeue
 );
-    `USE_FAST_BRAM reg [`LINE_ADDR_WIDTH-1:0] addr_table [MSHR_SIZE-1:0];
+    `USE_FAST_BRAM reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
    
    reg [MSHR_SIZE-1:0]            valid_table;
    reg [MSHR_SIZE-1:0]            ready_table;