Added CSR TID/WID reads
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24
rtl/interfaces/VX_csr_req_inter.v
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24
rtl/interfaces/VX_csr_req_inter.v
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@@ -0,0 +1,24 @@
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`include "../VX_define.v"
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`ifndef VX_CSR_REQ
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`define VX_CSR_REQ
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interface VX_csr_req_inter ();
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wire[`NT_M1:0] valid;
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wire[`NW_M1:0] warp_num;
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wire[4:0] rd;
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wire[1:0] wb;
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wire is_csr;
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wire[11:0] csr_address;
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wire csr_immed;
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wire[31:0] csr_mask;
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endinterface
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`endif
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21
rtl/interfaces/VX_csr_wb_inter.v
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21
rtl/interfaces/VX_csr_wb_inter.v
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@@ -0,0 +1,21 @@
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`include "../VX_define.v"
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`ifndef VX_CSR_WB_REQ
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`define VX_CSR_WB_REQ
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interface VX_csr_wb_inter ();
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wire[`NT_M1:0] valid;
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wire[`NW_M1:0] warp_num;
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wire[4:0] rd;
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wire[1:0] wb;
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wire[`NT_M1:0][31:0] csr_result;
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endinterface
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`endif
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@@ -1,18 +0,0 @@
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`include "../VX_define.v"
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`ifndef VX_CSR_W_REQ
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`define VX_CSR_W_REQ
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interface VX_csr_write_request_inter ();
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wire is_csr;
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wire[11:0] csr_address;
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wire[31:0] csr_result;
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endinterface
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`endif
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@@ -13,6 +13,8 @@ interface VX_gpu_inst_req_inter();
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wire is_split;
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wire is_barrier;
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wire pc_next;
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wire[`NT_M1:0][31:0] a_reg_data;
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wire[31:0] rd2;
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@@ -16,6 +16,13 @@ interface VX_warp_ctl_inter ();
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wire ebreak;
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wire is_split;
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wire[`NT_M1:0] split_new_mask;
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wire[`NT_M1:0] split_later_mask;
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wire[31:0] split_save_pc;
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endinterface
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