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This commit is contained in:
felsabbagh3
2019-10-18 01:46:38 -04:00
parent ccbb2acab5
commit 6b729fd2ea
9 changed files with 3 additions and 9 deletions
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98
rtl/simulate/VX_define.h Normal file
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#define NT 4
#define NT_M1 (NT-1)
#define NW 8
#define R_INST 51
#define L_INST 3
#define ALU_INST 19
#define S_INST 35
#define B_INST 99
#define LUI_INST 55
#define AUIPC_INST 23
#define JAL_INST 111
#define JALR_INST 103
#define SYS_INST 115
#define WB_ALU 1
#define WB_MEM 2
#define WB_JAL 3
#define NO_WB 0
#define RS2_IMMED 1
#define RS2_REG 0
#define NO_MEM_READ 7
#define LB_MEM_READ 0
#define LH_MEM_READ 1
#define LW_MEM_READ 2
#define LBU_MEM_READ 4
#define LHU_MEM_READ 5
#define NO_MEM_WRITE 7
#define SB_MEM_WRITE 0
#define SH_MEM_WRITE 1
#define SW_MEM_WRITE 2
#define NO_BRANCH 0
#define BEQ 1
#define BNE 2
#define BLT 3
#define BGT 4
#define BLTU 5
#define BGTU 6
#define NO_ALU 15
#define ADD 0
#define SUB 1
#define SLLA 2
#define SLT 3
#define SLTU 4
#define XOR 5
#define SRL 6
#define SRA 7
#define OR 8
#define AND 9
#define SUBU 10
#define LUI_ALU 11
#define AUIPC_ALU 12
#define CSR_ALU_RW 13
#define CSR_ALU_RS 14
#define CSR_ALU_RC 15
// WRITEBACK
#define WB_ALU 1
#define WB_MEM 2
#define WB_JAL 3
#define NO_WB 0
// JAL
#define JUMP 1
#define NO_JUMP 0
// STALLS
#define STALL 1
#define NO_STALL 0
#define TAKEN 1
#define NOT_TAKEN 0
#define ZERO_REG 0
// COLORS
#define GREEN "\033[32m"
#define RED "\033[31m"
#define DEFAULT "\033[39m"

233
rtl/simulate/ram.h Normal file
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#ifndef __RAM__
#define __RAM__
#include "string.h"
#include <stdint.h>
#include <cstdint>
class RAM{
public:
uint8_t* mem[1 << 12];
RAM(){
for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL;
}
~RAM(){
for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i];
}
void clear(){
for(uint32_t i = 0;i < (1 << 12);i++)
{
if(mem[i])
{
delete mem[i];
mem[i] = NULL;
}
}
}
uint8_t* get(uint32_t address){
if(mem[address >> 20] == NULL) {
uint8_t* ptr = new uint8_t[1024*1024];
for(uint32_t i = 0;i < 1024*1024;i+=4) {
ptr[i + 0] = 0xFF;
ptr[i + 1] = 0xFF;
ptr[i + 2] = 0xFF;
ptr[i + 3] = 0xFF;
}
mem[address >> 20] = ptr;
}
return &mem[address >> 20][address & 0xFFFFF];
}
void read(uint32_t address,uint32_t length, uint8_t *data){
for(unsigned i = 0;i < length;i++){
data[i] = (*this)[address + i];
}
}
void write(uint32_t address,uint32_t length, uint8_t *data){
for(unsigned i = 0;i < length;i++){
(*this)[address + i] = data[i];
}
}
void getBlock(uint32_t address, uint8_t *data)
{
uint32_t block_number = address & 0xffffff00; // To zero out block offset
uint32_t bytes_num = 256;
this->read(block_number, bytes_num, data);
}
void getWord(uint32_t address, uint32_t * data)
{
data[0] = 0;
uint8_t first = *get(address + 0);
uint8_t second = *get(address + 1);
uint8_t third = *get(address + 2);
uint8_t fourth = *get(address + 3);
// uint8_t hi = (uint8_t) *get(address + 0);
// std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << hi << "\n";
// hi = (uint8_t) *get(address + 1);
// std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << hi << "\n";
// hi = (uint8_t) *get(address + 2);
// std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << hi << "\n";
// hi = (uint8_t) *get(address + 3);
// std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << hi << "\n";
data[0] = (data[0] << 0) | fourth;
data[0] = (data[0] << 8) | third;
data[0] = (data[0] << 8) | second;
data[0] = (data[0] << 8) | first;
}
void writeWord(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 4; i++)
{
// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeHalf(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 2; i++)
{
// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeByte(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
(*this)[address] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
uint8_t& operator [](uint32_t address) {
return *get(address);
}
};
// MEMORY UTILS
uint32_t hti(char c) {
if (c >= 'A' && c <= 'F')
return c - 'A' + 10;
if (c >= 'a' && c <= 'f')
return c - 'a' + 10;
return c - '0';
}
uint32_t hToI(char *c, uint32_t size) {
uint32_t value = 0;
for (uint32_t i = 0; i < size; i++) {
value += hti(c[i]) << ((size - i - 1) * 4);
}
return value;
}
void loadHexImpl(std::string path,RAM* mem) {
mem->clear();
FILE *fp = fopen(&path[0], "r");
if(fp == 0){
std::cout << path << " not found" << std::endl;
}
//Preload 0x0 <-> 0x80000000 jumps
((uint32_t*)mem->get(0))[1] = 0xf1401073;
((uint32_t*)mem->get(0))[2] = 0x30101073;
((uint32_t*)mem->get(0))[3] = 0x800000b7;
((uint32_t*)mem->get(0))[4] = 0x000080e7;
((uint32_t*)mem->get(0x80000000))[0] = 0x00000097;
((uint32_t*)mem->get(0xb0000000))[0] = 0x01C02023;
// F00FFF10
((uint32_t*)mem->get(0xf00fff10))[0] = 0x12345678;
fseek(fp, 0, SEEK_END);
uint32_t size = ftell(fp);
fseek(fp, 0, SEEK_SET);
char* content = new char[size];
fread(content, 1, size, fp);
int offset = 0;
char* line = content;
// std::cout << "WHTA\n";
while (1) {
if (line[0] == ':') {
uint32_t byteCount = hToI(line + 1, 2);
uint32_t nextAddr = hToI(line + 3, 4) + offset;
uint32_t key = hToI(line + 7, 2);
switch (key) {
case 0:
for (uint32_t i = 0; i < byteCount; i++) {
unsigned add = nextAddr + i;
*(mem->get(add)) = hToI(line + 9 + i * 2, 2);
}
break;
case 2:
// cout << offset << endl;
offset = hToI(line + 9, 4) << 4;
break;
case 4:
// cout << offset << endl;
offset = hToI(line + 9, 4) << 16;
break;
default:
// cout << "??? " << key << endl;
break;
}
}
while (*line != '\n' && size != 0) {
line++;
size--;
}
if (size <= 1)
break;
line++;
size--;
}
if (content) delete[] content;
}
#endif

1
rtl/simulate/tb_debug.h Normal file
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#define VCD_OFF

93
rtl/simulate/test_bench.cpp Normal file
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#include "test_bench.h"
#define NUM_TESTS 46
int main(int argc, char **argv)
{
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
// Verilated::debug(1);
// bool passed = true;
// std::string tests[NUM_TESTS] = {
// "../../emulator/riscv_tests/rv32ui-p-add.hex",
// "../../emulator/riscv_tests/rv32ui-p-addi.hex",
// "../../emulator/riscv_tests/rv32ui-p-and.hex",
// "../../emulator/riscv_tests/rv32ui-p-andi.hex",
// "../../emulator/riscv_tests/rv32ui-p-auipc.hex",
// "../../emulator/riscv_tests/rv32ui-p-beq.hex",
// "../../emulator/riscv_tests/rv32ui-p-bge.hex",
// "../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
// "../../emulator/riscv_tests/rv32ui-p-blt.hex",
// "../../emulator/riscv_tests/rv32ui-p-bltu.hex",
// "../../emulator/riscv_tests/rv32ui-p-bne.hex",
// "../../emulator/riscv_tests/rv32ui-p-jal.hex",
// "../../emulator/riscv_tests/rv32ui-p-jalr.hex",
// "../../emulator/riscv_tests/rv32ui-p-lb.hex",
// "../../emulator/riscv_tests/rv32ui-p-lbu.hex",
// "../../emulator/riscv_tests/rv32ui-p-lh.hex",
// "../../emulator/riscv_tests/rv32ui-p-lhu.hex",
// "../../emulator/riscv_tests/rv32ui-p-lui.hex",
// "../../emulator/riscv_tests/rv32ui-p-lw.hex",
// "../../emulator/riscv_tests/rv32ui-p-or.hex",
// "../../emulator/riscv_tests/rv32ui-p-ori.hex",
// "../../emulator/riscv_tests/rv32ui-p-sb.hex",
// "../../emulator/riscv_tests/rv32ui-p-sh.hex",
// "../../emulator/riscv_tests/rv32ui-p-simple.hex",
// "../../emulator/riscv_tests/rv32ui-p-sll.hex",
// "../../emulator/riscv_tests/rv32ui-p-slli.hex",
// "../../emulator/riscv_tests/rv32ui-p-slt.hex",
// "../../emulator/riscv_tests/rv32ui-p-slti.hex",
// "../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
// "../../emulator/riscv_tests/rv32ui-p-sltu.hex",
// "../../emulator/riscv_tests/rv32ui-p-sra.hex",
// "../../emulator/riscv_tests/rv32ui-p-srai.hex",
// "../../emulator/riscv_tests/rv32ui-p-srl.hex",
// "../../emulator/riscv_tests/rv32ui-p-srli.hex",
// "../../emulator/riscv_tests/rv32ui-p-sub.hex",
// "../../emulator/riscv_tests/rv32ui-p-sw.hex",
// "../../emulator/riscv_tests/rv32ui-p-xor.hex",
// "../../emulator/riscv_tests/rv32ui-p-xori.hex",
// "../../emulator/riscv_tests/rv32um-p-div.hex",
// "../../emulator/riscv_tests/rv32um-p-divu.hex",
// "../../emulator/riscv_tests/rv32um-p-mul.hex",
// "../../emulator/riscv_tests/rv32um-p-mulh.hex",
// "../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
// "../../emulator/riscv_tests/rv32um-p-mulhu.hex",
// "../../emulator/riscv_tests/rv32um-p-rem.hex",
// "../../emulator/riscv_tests/rv32um-p-remu.hex"
// };
// for (int ii = 0; ii < NUM_TESTS; ii++)
// // for (int ii = 5; ii < 6; ii++)
// {
// std::cout << "TESTING: " << tests[ii] << '\n';
// Vortex v;
// bool curr = v.simulate(tests[ii]);
// if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl;
// if (!curr) std::cerr << RED << "Test Failed: " << tests[ii] << std::endl;
// passed = passed && curr;
// std::cerr << DEFAULT;
// }
// if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
// if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
Vortex v;
char testing[] = "../../kernel/vortex_test.hex";
bool curr = v.simulate(testing);
if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
return 0;
}

427
rtl/simulate/test_bench.h Normal file
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// C++ libraries
#include <utility>
#include <iostream>
#include <map>
#include <iterator>
#include <iomanip>
#include <fstream>
#include <unistd.h>
#include <vector>
#include <math.h>
#include <algorithm>
#include "VX_define.h"
#include "ram.h"
#include "VVortex.h"
#include "verilated.h"
#include "tb_debug.h"
#ifdef VCD_OUTPUT
#include <verilated_vcd_c.h>
#endif
class Vortex
{
public:
Vortex();
~Vortex();
bool simulate(std::string);
private:
void ProcessFile(void);
void print_stats(bool = true);
bool ibus_driver();
bool dbus_driver();
RAM ram;
VVortex * vortex;
unsigned start_pc;
long int curr_cycle;
bool stop;
bool unit_test;
std::string instruction_file_name;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
int stats_total_cycles;
int stats_fwd_stalls;
int stats_branch_stalls;
int debug_state;
int ibus_state;
int dbus_state;
int debug_return;
int debug_wait_num;
int debug_inst_num;
int debug_end_wait;
int debug_debugAddr;
double stats_sim_time;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
};
Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
{
this->vortex = new VVortex;
#ifdef VCD_OUTPUT
this->m_trace = new VerilatedVcdC;
this->vortex->trace(m_trace, 99);
this->m_trace->open("trace.vcd");
#endif
this->results.open("../results.txt");
}
Vortex::~Vortex()
{
#ifdef VCD_OUTPUT
m_trace->close();
#endif
this->results.close();
delete this->vortex;
}
void Vortex::ProcessFile(void)
{
loadHexImpl(this->instruction_file_name, &this->ram);
}
void Vortex::print_stats(bool cycle_test)
{
if (cycle_test)
{
this->results << std::left;
// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
else
{
this->results << std::left;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
uint32_t status;
ram.getWord(0, &status);
if (this->unit_test)
{
if (status == 1)
{
this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
} else
{
this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
}
}
else
{
this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
}
this->stats_static_inst = 0;
this->stats_dynamic_inst = -1;
this->stats_total_cycles = 0;
this->stats_fwd_stalls = 0;
this->stats_branch_stalls = 0;
}
bool Vortex::ibus_driver()
{
////////////////////// IBUS //////////////////////
unsigned new_PC;
bool stop = false;
uint32_t curr_inst = 0;
curr_inst = 0xdeadbeef;
new_PC = vortex->icache_request_pc_address;
ram.getWord(new_PC, &curr_inst);
vortex->icache_response_instruction = curr_inst;
// std::cout << std::hex << "IReq: " << vortex->icache_request_pc_address << "\tResp: " << curr_inst << "\n";
// printf("\n\n---------------------------------------------\n(%x) Inst: %x\n", new_PC, curr_inst);
// printf("\n");
////////////////////// IBUS //////////////////////
////////////////////// STATS //////////////////////
if (((((unsigned int)curr_inst) != 0) && (((unsigned int)curr_inst) != 0xffffffff)))
{
++stats_dynamic_inst;
stop = false;
} else
{
// printf("Ibus requesting stop: %x\n", curr_inst);
stop = true;
}
return stop;
}
bool Vortex::dbus_driver()
{
uint32_t data_read;
uint32_t data_write;
uint32_t addr;
// std::cout << "DBUS DRIVER\n" << std::endl;
////////////////////// DBUS //////////////////////
bool did = false;
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
{
if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid[curr_th])
{
did = true;
data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th];
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
if (addr == 0x00010000)
{
std::cerr << (char) data_write;
}
// if ((addr >= 0x810002cc) && (addr < 0x810002d0))
// {
// int index = (addr - 0x810002cc) / 4;
// // std::cerr << GREEN << "1done[" << index << "] = " << data_write << DEFAULT << "\n";
// }
// if ((addr >= 0x810059f4) && (addr < 0x810059f4))
// {
// int index = (addr - 0x810059f4) / 4;
// // std::cerr << RED << "2done[" << index << "] = " << data_write << DEFAULT << "\n";
// }
if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
{
data_write = ( data_write) & 0xFF;
ram.writeByte( addr, &data_write);
} else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE)
{
data_write = ( data_write) & 0xFFFF;
ram.writeHalf( addr, &data_write);
} else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE)
{
// printf("STORING %x in %x \n", data_write, addr);
data_write = data_write;
ram.writeWord( addr, &data_write);
}
}
}
// printf("----\n");
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
{
if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th])
{
did = true;
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
ram.getWord(addr, &data_read);
if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ)
{
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF);
} else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ)
{
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF);
} else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ)
{
// printf("Reading mem - Addr: %x = %x\n", addr, data_read);
// std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n";
// std::cout << std::dec;
vortex->in_cache_driver_out_data[curr_th] = data_read;
} else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
{
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF);
} else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ)
{
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF);
}
else
{
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
}
}
else
{
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
}
}
if (did && (NW > 1))
{
if (NW < NT)
{
this->stats_total_cycles += NT % (NW -1);
}
}
// printf("******\n");
return false;
}
bool Vortex::simulate(std::string file_to_simulate)
{
this->instruction_file_name = file_to_simulate;
// this->results << "\n****************\t" << file_to_simulate << "\t****************\n";
this->ProcessFile();
// auto start_time = std::chrono::high_resolution_clock::now();
static bool stop = false;
static int counter = 0;
counter = 0;
stop = false;
// auto start_time = clock();
// vortex->reset = 1;
// vortex->reset = 0;
unsigned curr_inst;
unsigned new_PC;
// while (this->stop && (!(stop && (counter > 5))))
// {
// // std::cout << "************* Cycle: " << cycle << "\n";
// bool istop = ibus_driver();
// bool dstop = !dbus_driver();
// vortex->clk = 1;
// vortex->eval();
// vortex->clk = 0;
// vortex->eval();
// stop = istop && dstop;
// if (stop)
// {
// counter++;
// } else
// {
// counter = 0;
// }
// cycle++;
// }
bool istop;
bool dstop;
bool cont = false;
// for (int i = 0; i < 500; i++)
vortex->clk = 0;
vortex->eval();
// unsigned cycles;
counter = 0;
this->stats_total_cycles = 10;
while (this->stop && ((counter < 6)))
// while (this->stats_total_cycles < 10)
{
// std::cout << "Counter: " << counter << "\n";
// if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
// dstop = !dbus_driver();
vortex->clk = 1;
vortex->eval();
#ifdef VCD_OUTPUT
m_trace->dump(2*this->stats_total_cycles);
#endif
istop = ibus_driver();
dstop = !dbus_driver();
vortex->clk = 0;
vortex->eval();
#ifdef VCD_OUTPUT
m_trace->dump((2*this->stats_total_cycles)+1);
#endif
// stop = istop && dstop;
stop = vortex->out_ebreak;
if (stop || cont)
// if (istop)
{
cont = true;
counter++;
} else
{
counter = 0;
}
++stats_total_cycles;
}
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
// int status = (unsigned int) vortex->Vortex__DOT__vx_front_end__DOT__vx_decode__DOT__vx_grp_wrapper__DOT__genblk2__BRA__0__KET____DOT__vx_gpr__DOT__first_ram__DOT__GPR[28][0] & 0xf;
// std::cout << "Something: " << result << '\n';
// uint32_t status;
// ram.getWord(0, &status);
this->print_stats();
// return (status == 1);
return (1 == 1);
}