This commit is contained in:
felsabbagh3
2019-10-18 01:46:38 -04:00
parent ccbb2acab5
commit 6b729fd2ea
9 changed files with 3 additions and 9 deletions

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@@ -1,10 +1,10 @@
all: RUNFILE
INCLUDE=-I. -I../models/memory/cln28hpc/rf2_32x128_wm1/ -I/usr/local/systemc/ -Iinterfaces/ -Ipipe_regs/
INCLUDE=-I. -I../models/memory/cln28hpc/rf2_32x128_wm1/ -I/usr/local/systemc/ -Iinterfaces/ -Ipipe_regs/ -Isimulate
FILE=Vortex.v
EXE=--exe test_bench.cpp
EXE=--exe ./simulate/test_bench.cpp
COMP=--compiler gcc

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@@ -43,9 +43,7 @@ interface VX_exec_unit_req_inter ();
// CSR info
wire is_csr;
wire[11:0] csr_address;
/* verilator lint_off UNUSED */
wire csr_immed;
/* verilator lint_on UNUSED */
wire[31:0] csr_mask;
endinterface

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@@ -6,11 +6,8 @@
`define VX_FWD_CSR_RSP
interface VX_forward_csr_response_inter ();
/* verilator lint_off UNUSED */
wire csr_fwd;
wire[31:0] csr_fwd_data;
/* verilator lint_on UNUSED */
endinterface

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@@ -9,9 +9,7 @@ interface VX_frE_to_bckE_req_inter ();
wire[11:0] csr_address;
wire is_csr;
/* verilator lint_off UNUSED */
wire csr_immed;
/* verilator lint_on UNUSED */
wire[31:0] csr_mask;
wire[4:0] rd;
wire[4:0] rs1;

1
rtl/simulate/tb_debug.h Normal file
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@@ -0,0 +1 @@
#define VCD_OFF