Merge branch 'master' of https://github.gatech.edu/casl/Vortex
This commit is contained in:
@@ -62,12 +62,12 @@ Install Verilator
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Install Vortex
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$ git clone https://github.gatech.edu/casl/Vortex.git
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$ git clone --recursive https://github.gatech.edu/casl/Vortex.git
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$ cd Vortex
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$ make
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Quick Test running SGEMM kernel
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$ cd /Vortex/benchmarks/opencl/sgemm
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$ cd /Vortex/benchmarks/opencl/vecadd
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$ make
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$ make run
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$ make run-rtlsim
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2
benchmarks/riscv_tests/Makefile
Normal file
2
benchmarks/riscv_tests/Makefile
Normal file
@@ -0,0 +1,2 @@
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run:
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$(MAKE) -C isa run
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6
benchmarks/riscv_tests/isa/Makefile
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6
benchmarks/riscv_tests/isa/Makefile
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@@ -0,0 +1,6 @@
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TESTS := $(wildcard *.hex)
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#VTESTS := $(wildcard *-v-*.hex)
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#TESTS := $(filter-out $(VTESTS) rv32ud-p-fclass.hex, $(TESTS))
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run:
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cd ../../../hw/simulate/obj_dir && ./VVortex -f $(foreach test,$(TESTS),../../../benchmarks/riscv_tests/isa/$(test))
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14
driver/tests/Makefile
Normal file
14
driver/tests/Makefile
Normal file
@@ -0,0 +1,14 @@
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all:
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$(MAKE) -C basic
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$(MAKE) -C demo
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run:
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$(MAKE) -C basic run-rtlsim
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$(MAKE) -C basic run-simx
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$(MAKE) -C demo run-rtlsim
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$(MAKE) -C demo run-simx
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clean:
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$(MAKE) -C basic clean
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$(MAKE) -C demo clean
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@@ -143,18 +143,42 @@ int main(int argc, char **argv) {
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#endif
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} else {
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bool passed = true;
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char* test = argv[2];
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std::vector<std::string> tests(argv+2, argv+argc);
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for (std::string test : tests) {
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std::cerr << DEFAULT << "\n---------------------------------------\n";
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std::cerr << test << std::endl;
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RAM ram;
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Simulator simulator;
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simulator.attach_ram(&ram);
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simulator.load_ihex(test.c_str());
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simulator.run();
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bool status = (1 == simulator.get_last_wb_value(3));
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if (status) std::cerr << GREEN << "Test Passed: " << test << std::endl;
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if (!status) std::cerr << RED << "Test Failed: " << test << std::endl;
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std::cerr << DEFAULT;
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passed = passed && status;
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if (!passed)
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break;
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}
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std::cerr << test << std::endl;
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RAM ram;
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Simulator simulator;
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simulator.attach_ram(&ram);
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simulator.load_ihex(test);
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simulator.run();
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// char* test = argv[2];
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// std::cerr << test << std::endl;
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// RAM ram;
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// Simulator simulator;
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// simulator.attach_ram(&ram);
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// simulator.load_ihex(test);
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// simulator.run();
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return 0;
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}
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}
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}
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@@ -6,11 +6,11 @@ all:
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$(MAKE) -C vecadd
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run:
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cd simple && $(MAKE) run
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cd dev && $(MAKE) run
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cd hello && $(MAKE) run
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cd nlTest && $(MAKE) run
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cd vecadd && $(MAKE) run
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$(MAKE) -C simple run
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$(MAKE) -C dev run
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$(MAKE) -C hello run
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$(MAKE) -C nlTest run
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$(MAKE) -C vecadd run
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clean:
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$(MAKE) -C simple clean
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