Passing Most tests

rtl/Makefile

@@ -5,7 +5,7 @@ all: RUNFILE
 
 
 VERILATOR:
-	verilator -Wall -cc vortex.v VX_f_d_reg.v VX_fetch.v --exe test_bench.cpp 
+	verilator -Wall -cc Vortex.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp 
 
 RUNFILE: VERILATOR
 	(cd obj_dir && make -j -f Vvortex.mk)

rtl/VX_csr_handler.v

@@ -0,0 +1,73 @@
+
+
+module VX_csr_handler (
+		input wire        clk,
+		input wire[11:0]  in_decode_csr_address, // done
+		input wire[11:0]  in_mem_csr_address,
+		input wire        in_mem_is_csr,
+		/* verilator lint_off UNUSED */
+		input wire[31:0]  in_mem_csr_result,
+		/* verilator lint_on UNUSED */
+		input wire        in_wb_valid,
+		output wire[31:0] out_decode_csr_data // done
+	);
+
+
+		reg[11:0] csr[4095:0];
+		reg[63:0] cycle;
+		reg[63:0] instret;
+		reg[11:0] decode_csr_address;
+
+
+		wire read_cycle;
+		wire read_cycleh;
+		wire read_instret;
+		wire read_instreth;
+
+		initial begin
+			cycle              = 0;
+			instret            = 0;
+			decode_csr_address = 0;
+		end
+
+
+		always @(posedge clk) begin
+			cycle              <= cycle   + 1;
+			decode_csr_address <= in_decode_csr_address;
+			if (in_wb_valid) begin
+				instret <= instret + 1;
+			end
+		end
+
+
+		always @(posedge clk) begin
+			if(in_mem_is_csr) begin
+				csr[in_mem_csr_address] <= in_mem_csr_result[11:0];
+			end
+		end
+
+
+		assign read_cycle    = decode_csr_address == 12'hC00;
+		assign read_cycleh   = decode_csr_address == 12'hC80;
+		assign read_instret  = decode_csr_address == 12'hC02;
+		assign read_instreth = decode_csr_address == 12'hC82;
+
+
+    	assign out_decode_csr_data = read_cycle ? cycle[31:0] :
+    									read_cycleh ? cycle[63:32] : 
+    											read_instret ? instret[31:0] :
+    													read_instreth ? instret[63:32] : 
+    															{{20{1'b0}}, csr[decode_csr_address]};
+
+
+
+
+
+endmodule // VX_csr_handler
+
+
+
+
+
+
+

rtl/VX_d_e_reg.v

@@ -0,0 +1,160 @@
+
+
+`include "VX_define.v"
+
+module VX_d_e_reg (
+		input wire       clk,
+		input wire[4:0]  in_rd,
+		input wire[4:0]  in_rs1,
+		input wire[31:0] in_rd1,
+		input wire[4:0]  in_rs2,
+		input wire[31:0] in_rd2,
+		input wire[3:0]  in_alu_op,
+		input wire[1:0]  in_wb,
+		input wire       in_rs2_src, // NEW
+		input wire[31:0] in_itype_immed, // new
+		input wire[2:0]  in_mem_read, // NEW
+		input wire[2:0]  in_mem_write,
+		input wire[31:0] in_PC_next,
+		input wire[2:0]  in_branch_type,
+		input wire       in_fwd_stall,
+		input wire       in_branch_stall,
+		input wire[19:0] in_upper_immed,
+		input wire[11:0] in_csr_address, // done
+		input wire       in_is_csr, // done
+		input wire[31:0] in_csr_mask, // done
+		input wire[31:0] in_curr_PC,
+		input wire       in_jal,
+		input wire[31:0] in_jal_offset,
+		input wire       in_freeze,
+		input wire       in_valid,
+
+		output wire[11:0] out_csr_address, // done
+		output wire       out_is_csr, // done
+		output wire[31:0] out_csr_mask, // done
+		output wire[4:0]  out_rd,
+		output wire[4:0]  out_rs1,
+		output wire[31:0] out_rd1,
+		output wire[4:0]  out_rs2,
+		output wire[31:0] out_rd2,
+		output wire[3:0]  out_alu_op,
+		output wire[1:0]  out_wb,
+		output wire       out_rs2_src, // NEW
+		output wire[31:0] out_itype_immed, // new
+		output wire[2:0]  out_mem_read,
+		output wire[2:0]  out_mem_write,
+		output wire[2:0]  out_branch_type,
+		output wire[19:0] out_upper_immed,
+		output wire[31:0] out_curr_PC,
+		output wire       out_jal,
+		output wire[31:0] out_jal_offset,
+		output wire[31:0] out_PC_next,
+		output wire       out_valid
+	);
+
+
+		reg[4:0]  rd;
+		reg[4:0]  rs1;
+		reg[31:0] rd1;
+		reg[4:0]  rs2;
+		reg[31:0] rd2;
+		reg[3:0]  alu_op;
+		reg[1:0]  wb;
+		reg[31:0] PC_next_out;
+		reg       rs2_src;
+		reg[31:0] itype_immed;
+		reg[2:0]  mem_read;
+		reg[2:0]  mem_write;
+		reg[2:0]  branch_type;
+		reg[19:0] upper_immed;
+		reg[11:0] csr_address;
+		reg       is_csr;
+		reg[31:0] csr_mask;
+		reg[31:0] curr_PC;
+		reg       jal;
+		reg[31:0] jal_offset;
+		reg       valid;
+
+
+		initial begin
+			rd          = 0;
+			rs1         = 0;
+			rd1         = 0;
+			rs2         = 0;
+			rd2         = 0;
+			alu_op      = 0;
+			wb          = `NO_WB;
+			PC_next_out = 0;
+			rs2_src     = 0;
+			itype_immed = 0;
+			mem_read    = `NO_MEM_READ;
+			mem_write   = `NO_MEM_WRITE;
+			branch_type = `NO_BRANCH;
+			upper_immed = 0;
+			csr_address = 0;
+			is_csr      = 0;
+			csr_mask    = 0;
+			curr_PC     = 0;
+			jal         = `NO_JUMP;
+			jal_offset  = 0;
+			valid       = 0;
+		end
+
+		wire stalling;
+
+		assign stalling = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL);
+
+		assign out_rd          = rd;
+		assign out_rs1         = rs1;
+		assign out_rd1         = rd1;
+		assign out_rs2         = rs2;
+		assign out_rd2         = rd2;
+		assign out_alu_op      = alu_op;
+		assign out_wb          = wb;
+		assign out_PC_next     = PC_next_out;
+		assign out_rs2_src     = rs2_src;
+		assign out_itype_immed = itype_immed;
+		assign out_mem_read    = mem_read;
+		assign out_mem_write   = mem_write;
+		assign out_branch_type = branch_type;
+		assign out_upper_immed = upper_immed;
+		assign out_csr_address = csr_address;
+		assign out_is_csr      = is_csr;
+		assign out_csr_mask    = csr_mask;
+		assign out_jal         = jal;
+		assign out_jal_offset  = jal_offset;
+		assign out_curr_PC     = curr_PC;
+		assign out_valid       = valid;
+
+
+		always @(posedge clk) begin
+			if (in_freeze == 1'h0) begin
+				rd          <= stalling ? 5'h0         : in_rd;
+				rs1         <= stalling ? 5'h0         : in_rs1;
+				rd1         <= stalling ? 32'h0        : in_rd1;
+				rs2         <= stalling ? 5'h0         : in_rs2;
+				rd2         <= stalling ? 32'h0        : in_rd2;
+				alu_op      <= stalling ? `NO_ALU      : in_alu_op;
+				wb          <= stalling ? `NO_WB       : in_wb;
+				PC_next_out <= stalling ? 32'h0        : in_PC_next;
+				rs2_src     <= stalling ? `RS2_REG     : in_rs2_src;
+				itype_immed <= stalling ? 32'hdeadbeef : in_itype_immed;
+				mem_read    <= stalling ? `NO_MEM_READ : in_mem_read;
+				mem_write   <= stalling ? `NO_MEM_WRITE: in_mem_write;
+				branch_type <= stalling ? `NO_BRANCH   : in_branch_type;
+				upper_immed <= stalling ? 20'h0        : in_upper_immed;
+				csr_address <= stalling ? 12'h0        : in_csr_address;
+				is_csr      <= stalling ? 1'h0         : in_is_csr;
+				csr_mask    <= stalling ? 32'h0        : in_csr_mask;
+				jal         <= stalling ? `NO_JUMP     : in_jal;
+				jal_offset  <= stalling ? 32'h0        : in_jal_offset;
+				curr_PC     <= stalling ? 32'h0        : in_curr_PC;
+				valid       <= stalling ? 1'b0         : in_valid;
+			end
+		end
+
+endmodule
+
+
+
+

rtl/VX_decode.v

@@ -1,73 +1,12 @@
 
-
+`include "VX_define.v"
-`define R_INST 7'd51
-`define L_INST 7'd3
-`define ALU_INST 7'd19
-`define S_INST 7'd35
-`define B_INST 7'd99
-`define LUI_INST 7'd55
-`define AUIPC_INST 7'd23
-`define JAL_INST 7'd111
-`define JALR_INST 7'd103
-`define SYS_INST 7'd115
-
-
-`define WB_ALU 2'h1
-`define WB_MEM 2'h2
-`define WB_JAL 2'h3
-`define NO_WB  2'h0
-
-
-`define RS2_IMMED 1
-`define RS2_REG 0
-
-
-`define NO_MEM_READ  3'h7
-`define LB_MEM_READ  3'h0
-`define LH_MEM_READ  3'h1
-`define LW_MEM_READ  3'h2
-`define LBU_MEM_READ 3'h4
-`define LHU_MEM_READ 3'h5
-
-
-`define NO_MEM_WRITE 3'h7
-`define SB_MEM_WRITE 3'h0
-`define SH_MEM_WRITE 3'h1
-`define SW_MEM_WRITE 3'h2
-
-
-`define NO_BRANCH 3'h0
-`define BEQ 3'h1
-`define BNE 3'h2
-`define BLT 3'h3
-`define BGT 3'h4
-`define BLTU 3'h5
-`define BGTU 3'h6
-
-
-`define NO_ALU 4'd15
-`define ADD 4'd0
-`define SUB 4'd1
-`define SLLA 4'd2
-`define SLT 4'd3
-`define SLTU 4'd4
-`define XOR 4'd5
-`define SRL 4'd6
-`define SRA 4'd7
-`define OR 4'd8
-`define AND 4'd9
-`define SUBU 4'd10
-`define LUI_ALU 4'd11
-`define AUIPC_ALU 4'd12
-`define CSR_ALU_RW 4'd13
-`define CSR_ALU_RS 4'd14
-`define CSR_ALU_RC 4'd15
 
 module VX_decode(
 	// Fetch Inputs
 	input wire        clk,
 	input wire[31:0]  in_instruction,
 	input wire[31:0]  in_curr_PC,
+	input wire        in_valid,
 	// WriteBack inputs
 	input wire[31:0]  in_write_data,
 	input wire[4:0]   in_rd,
@@ -100,7 +39,8 @@ module VX_decode(
 	output reg        out_jal,
 	output reg[31:0]  out_jal_offset,
 	output reg[19:0]  out_upper_immed,
-	output wire[31:0] out_PC_next
+	output wire[31:0] out_PC_next,
+	output wire       out_valid
 );
 
 		wire[6:0]  curr_opcode;
@@ -167,6 +107,8 @@ module VX_decode(
 			.out_src2_data(rd2_register)
 		);
 
+		assign out_valid = in_valid;
+
 		assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0);
 		assign curr_opcode    = in_instruction[6:0];
 

rtl/VX_define.h

@@ -0,0 +1,102 @@
+
+
+
+#define R_INST 51
+#define L_INST 3
+#define ALU_INST 19
+#define S_INST 35
+#define B_INST 99
+#define LUI_INST 55
+#define AUIPC_INST 23
+#define JAL_INST 111
+#define JALR_INST 103
+#define SYS_INST 115
+
+
+#define WB_ALU 1
+#define WB_MEM 2
+#define WB_JAL 3
+#define NO_WB  0
+
+
+#define RS2_IMMED 1
+#define RS2_REG 0
+
+
+#define NO_MEM_READ  7
+#define LB_MEM_READ  0
+#define LH_MEM_READ  1
+#define LW_MEM_READ  2
+#define LBU_MEM_READ 4
+#define LHU_MEM_READ 5
+
+
+#define NO_MEM_WRITE 7
+#define SB_MEM_WRITE 0
+#define SH_MEM_WRITE 1
+#define SW_MEM_WRITE 2
+
+
+#define NO_BRANCH 0
+#define BEQ 1
+#define BNE 2
+#define BLT 3
+#define BGT 4
+#define BLTU 5
+#define BGTU 6
+
+
+#define NO_ALU 15
+#define ADD 0
+#define SUB 1
+#define SLLA 2
+#define SLT 3
+#define SLTU 4
+#define XOR 5
+#define SRL 6
+#define SRA 7
+#define OR 8
+#define AND 9
+#define SUBU 10
+#define LUI_ALU 11
+#define AUIPC_ALU 12
+#define CSR_ALU_RW 13
+#define CSR_ALU_RS 14
+#define CSR_ALU_RC 15
+
+
+
+// WRITEBACK
+#define WB_ALU 1
+#define WB_MEM 2
+#define WB_JAL 3
+#define NO_WB  0
+
+
+// JAL
+#define JUMP 1
+#define NO_JUMP 0
+
+// STALLS
+#define STALL 1
+#define NO_STALL 0
+
+
+#define TAKEN 1
+#define NOT_TAKEN 0
+
+
+#define ZERO_REG 0
+
+
+// COLORS
+#define GREEN "\033[32m"
+#define RED "\033[31m"
+#define DEFAULT "\033[39m"
+
+
+
+
+
+
+

rtl/VX_define.v

@@ -0,0 +1,97 @@
+
+
+
+`define R_INST 7'd51
+`define L_INST 7'd3
+`define ALU_INST 7'd19
+`define S_INST 7'd35
+`define B_INST 7'd99
+`define LUI_INST 7'd55
+`define AUIPC_INST 7'd23
+`define JAL_INST 7'd111
+`define JALR_INST 7'd103
+`define SYS_INST 7'd115
+
+
+`define WB_ALU 2'h1
+`define WB_MEM 2'h2
+`define WB_JAL 2'h3
+`define NO_WB  2'h0
+
+
+`define RS2_IMMED 1
+`define RS2_REG 0
+
+
+`define NO_MEM_READ  3'h7
+`define LB_MEM_READ  3'h0
+`define LH_MEM_READ  3'h1
+`define LW_MEM_READ  3'h2
+`define LBU_MEM_READ 3'h4
+`define LHU_MEM_READ 3'h5
+
+
+`define NO_MEM_WRITE 3'h7
+`define SB_MEM_WRITE 3'h0
+`define SH_MEM_WRITE 3'h1
+`define SW_MEM_WRITE 3'h2
+
+
+`define NO_BRANCH 3'h0
+`define BEQ 3'h1
+`define BNE 3'h2
+`define BLT 3'h3
+`define BGT 3'h4
+`define BLTU 3'h5
+`define BGTU 3'h6
+
+
+`define NO_ALU 4'd15
+`define ADD 4'd0
+`define SUB 4'd1
+`define SLLA 4'd2
+`define SLT 4'd3
+`define SLTU 4'd4
+`define XOR 4'd5
+`define SRL 4'd6
+`define SRA 4'd7
+`define OR 4'd8
+`define AND 4'd9
+`define SUBU 4'd10
+`define LUI_ALU 4'd11
+`define AUIPC_ALU 4'd12
+`define CSR_ALU_RW 4'd13
+`define CSR_ALU_RS 4'd14
+`define CSR_ALU_RC 4'd15
+
+
+
+// WRITEBACK
+`define WB_ALU 2'h1
+`define WB_MEM 2'h2
+`define WB_JAL 2'h3
+`define NO_WB  2'h0
+
+
+// JAL
+`define JUMP 1'h1
+`define NO_JUMP 1'h0
+
+// STALLS
+`define STALL 1'h1
+`define NO_STALL 1'h0
+
+
+`define TAKEN 1'b1
+`define NOT_TAKEN 1'b0
+
+
+`define ZERO_REG 5'h0
+
+
+
+
+
+
+
+

rtl/VX_e_m_reg.v

@@ -0,0 +1,146 @@
+
+
+`include "VX_define.v"
+
+
+module VX_e_m_reg (
+		input wire        clk,
+		input wire[31:0]  in_alu_result,
+		input wire[4:0]   in_rd,
+		input wire[1:0]   in_wb,
+		input wire[4:0]   in_rs1,
+		input wire[31:0]  in_rd1,
+		input wire[4:0]   in_rs2,
+		input wire[31:0]  in_rd2,
+		input wire[2:0]   in_mem_read, // NEW
+		input wire[2:0]   in_mem_write, // NEW
+		input wire[31:0]  in_PC_next,
+		input wire[11:0]  in_csr_address,
+		input wire        in_is_csr,
+		input wire[31:0]  in_csr_result,
+		input wire[31:0]  in_curr_PC,
+		input wire[31:0]  in_branch_offset,
+		input wire[2:0]   in_branch_type,
+		input wire        in_jal,
+		input wire[31:0]  in_jal_dest,
+		input wire        in_freeze,
+		input wire        in_valid,
+
+		output wire[11:0] out_csr_address,
+		output wire       out_is_csr,
+		output wire[31:0] out_csr_result,
+		output wire[31:0] out_alu_result,
+		output wire[4:0]  out_rd,
+		output wire[1:0]  out_wb,
+		output wire[4:0]  out_rs1,
+		output wire[31:0] out_rd1,
+		output wire[31:0] out_rd2,
+		output wire[4:0]  out_rs2,
+		output wire[2:0]  out_mem_read,
+		output wire[2:0]  out_mem_write,
+		output wire[31:0] out_curr_PC,
+		output wire[31:0] out_branch_offset,
+		output wire[2:0]  out_branch_type,
+		output wire       out_jal,
+		output wire[31:0] out_jal_dest,
+		output wire[31:0] out_PC_next,
+		output wire       out_valid
+	);
+
+
+		reg[31:0] alu_result;
+		reg[4:0]  rd;
+		reg[4:0]  rs1;
+		reg[31:0] rd1;
+		reg[4:0]  rs2;
+		reg[31:0] rd2;
+		reg[1:0]  wb;
+		reg[31:0] PC_next;
+		reg[2:0]  mem_read;
+		reg[2:0]  mem_write;
+		reg[11:0] csr_address;
+		reg       is_csr;
+		reg[31:0] csr_result;
+		reg[31:0] curr_PC;
+		reg[31:0] branch_offset;
+		reg[2:0]  branch_type;
+		reg       jal;
+		reg[31:0] jal_dest;
+		reg       valid;
+
+
+		initial begin
+			alu_result    = 0;
+			rd            = 0;
+			rs1           = 0;
+			rd1           = 0;
+			rs2           = 0;
+			rd2           = 0;
+			wb            = 0;
+			PC_next       = 0;
+			mem_read      = `NO_MEM_READ;
+			mem_write     = `NO_MEM_WRITE;
+			csr_address   = 0;
+			is_csr        = 0;
+			csr_result    = 0;
+			curr_PC       = 0;
+			branch_offset = 0;
+			branch_type   = 0;
+			jal           = `NO_JUMP;
+			jal_dest      = 0;
+			valid         = 0;
+		end
+
+
+
+		assign out_alu_result    = alu_result;
+		assign out_rd            = rd;
+		assign out_rs1           = rs1;
+		assign out_rs2           = rs2;
+		assign out_wb            = wb;
+		assign out_PC_next       = PC_next;
+		assign out_mem_read      = mem_read;
+		assign out_mem_write     = mem_write;
+		assign out_rd1           = rd1;
+		assign out_rd2           = rd2;
+		assign out_csr_address   = csr_address;
+		assign out_is_csr        = is_csr;
+		assign out_csr_result    = csr_result;
+		assign out_curr_PC       = curr_PC;
+		assign out_branch_offset = branch_offset;
+		assign out_branch_type   = branch_type;
+		assign out_jal           = jal;
+		assign out_jal_dest      = jal_dest;
+		assign out_valid         = valid;
+		
+
+		always @(posedge clk) begin
+			if(in_freeze == 1'b0) begin
+				alu_result    <= in_alu_result;
+				rd            <= in_rd;
+				rs1           <= in_rs1;
+				rs2           <= in_rs2;
+				wb            <= in_wb;
+				PC_next       <= in_PC_next;
+				mem_read      <= in_mem_read;
+				mem_write     <= in_mem_write;
+				rd1           <= in_rd1;
+				rd2           <= in_rd2;
+				csr_address   <= in_csr_address;
+				is_csr        <= in_is_csr;
+				csr_result    <= in_csr_result;
+				curr_PC       <= in_curr_PC;
+				branch_offset <= in_branch_offset;
+				branch_type   <= in_branch_type;
+				jal           <= in_jal;
+				jal_dest      <= in_jal_dest;
+				valid         <= in_valid;
+			end
+		end
+
+endmodule // VX_e_m_reg
+
+
+
+
+

rtl/VX_execute.v

@@ -0,0 +1,185 @@
+
+`include "VX_define.v"
+
+module VX_execute (
+		input wire[4:0]   in_rd,
+		input wire[4:0]   in_rs1,
+		input wire[31:0]  in_rd1,
+		input wire[4:0]   in_rs2,
+		input wire[31:0]  in_rd2,
+		input wire[3:0]   in_alu_op,
+		input wire[1:0]   in_wb,
+		input wire        in_rs2_src, // NEW
+		input wire[31:0]  in_itype_immed, // new
+		input wire[2:0]   in_mem_read, // NEW
+		input wire[2:0]   in_mem_write, // NEW
+		input wire[31:0]  in_PC_next,
+		input wire[2:0]   in_branch_type,
+		input wire[19:0]  in_upper_immed,
+		input wire[11:0]  in_csr_address, // done
+		input wire        in_is_csr, // done
+		input wire[31:0]  in_csr_data, // done
+		input wire[31:0]  in_csr_mask, // done
+		input wire        in_jal,
+		input wire[31:0]  in_jal_offset,
+		input wire[31:0]  in_curr_PC,
+		input wire        in_valid,
+
+		output wire[11:0] out_csr_address,
+		output wire       out_is_csr,
+		output reg[31:0]  out_csr_result,
+		output reg[31:0]  out_alu_result,
+		output wire[4:0]  out_rd,
+		output wire[1:0]  out_wb,
+		output wire[4:0]  out_rs1,
+		output wire[31:0] out_rd1,
+		output wire[4:0]  out_rs2,
+		output wire[31:0] out_rd2,
+		output wire[2:0]  out_mem_read,
+		output wire[2:0]  out_mem_write,
+		output wire       out_jal,
+		output wire[31:0] out_jal_dest,
+		output wire[31:0] out_branch_offset,
+		output wire       out_branch_stall,
+		output wire[31:0] out_PC_next,
+		output wire       out_valid
+	);
+
+
+
+		wire which_in2;
+
+		wire[31:0] ALU_in1;
+		wire[31:0] ALU_in2;
+		wire[31:0] upper_immed;
+
+
+		assign which_in2  = in_rs2_src == `RS2_IMMED;
+
+		assign ALU_in1 = in_rd1;
+
+		assign ALU_in2 = which_in2 ? in_itype_immed : in_rd2;
+
+
+		assign upper_immed = {in_upper_immed, {12{1'b0}}};
+		assign out_jal_dest = $signed(in_rd1) + $signed(in_jal_offset);
+		assign out_jal      = in_jal;
+
+
+		always @(*) begin
+			case(in_alu_op)
+				`ADD:
+					begin
+						out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
+						out_csr_result = 32'hdeadbeef;
+					end
+				`SUB:
+					begin
+						out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);
+						out_csr_result = 32'hdeadbeef;
+					end
+				`SLLA:
+					begin
+						out_alu_result = ALU_in1 << ALU_in2;
+						out_csr_result = 32'hdeadbeef;
+					end
+				`SLT:
+					begin
+						out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0;
+						out_csr_result = 32'hdeadbeef;
+					end
+				`SLTU:
+					begin
+
+						out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0;
+						out_csr_result = 32'hdeadbeef;
+					end
+				`XOR:
+					begin
+						out_alu_result = ALU_in1 ^ ALU_in2;
+						out_csr_result = 32'hdeadbeef;
+					end
+				`SRL:
+					begin
+						out_alu_result = ALU_in1 >> ALU_in2;
+						out_csr_result = 32'hdeadbeef;
+					end
+				`SRA:
+					begin
+						out_alu_result    = $signed(ALU_in1)  >> ALU_in2;
+						out_csr_result    = 32'hdeadbeef;
+					end
+				`OR:
+					begin
+						out_alu_result = ALU_in1 | ALU_in2;
+						out_csr_result = 32'hdeadbeef;
+					end
+				`AND:
+					begin
+						out_alu_result = ALU_in2 & ALU_in1;
+						out_csr_result = 32'hdeadbeef;
+					end
+				`SUBU:
+					begin
+						if (ALU_in1 >= ALU_in2) begin
+							out_alu_result = 32'h0;
+						end else begin
+							out_alu_result = 32'hffffffff;
+
+						end
+						out_csr_result = 32'hdeadbeef;
+					end
+				`LUI_ALU:
+					begin
+						out_alu_result = upper_immed;
+						out_csr_result = 32'hdeadbeef;
+					end
+				`AUIPC_ALU:
+					begin
+						out_alu_result = $signed(in_curr_PC) + $signed(upper_immed);
+						out_csr_result = 32'hdeadbeef;
+					end
+				`CSR_ALU_RW:
+					begin
+						out_alu_result = in_csr_data;
+						out_csr_result = in_csr_mask;
+					end
+				`CSR_ALU_RS:
+					begin
+						out_alu_result = in_csr_data;
+						out_csr_result = in_csr_data | in_csr_mask;
+					end
+				`CSR_ALU_RC:
+					begin
+						out_alu_result = in_csr_data;
+						out_csr_result = in_csr_data & (32'hFFFFFFFF - in_csr_mask);
+					end
+				default:
+					begin
+						out_alu_result = 32'h0;
+						out_csr_result = 32'hdeadbeef;
+					end
+			endcase // in_alu_op
+		end
+
+
+		assign out_branch_stall = ((in_branch_type != `NO_BRANCH) || in_jal ) ? `STALL : `NO_STALL;
+
+
+
+		assign out_rd            = in_rd;
+		assign out_wb            = in_wb;
+		assign out_mem_read      = in_mem_read;
+		assign out_mem_write     = in_mem_write;
+		assign out_rs1           = in_rs1;
+		assign out_rd1           = in_rd1;
+		assign out_rd2           = in_rd2;
+		assign out_rs2           = in_rs2;
+		assign out_PC_next       = in_PC_next;
+		assign out_is_csr        = in_is_csr;
+		assign out_csr_address   = in_csr_address;
+		assign out_branch_offset = in_itype_immed;
+		assign out_valid         = in_valid;
+
+
+endmodule // VX_execute

rtl/VX_f_d_reg.v

@@ -14,9 +14,9 @@ module VX_f_d_reg (
 	  output wire       out_valid
 );
 
-	always @(posedge clk) begin
+	// always @(posedge clk) begin
-		$display("Fetch Inst: %d\tDecode Inst: %d", in_instruction, out_instruction);
+		// $display("Fetch Inst: %d\tDecode Inst: %d", in_instruction, out_instruction);
-	end
+	// end
 
 	reg[31:0] instruction;
 	reg[31:0] curr_PC;

rtl/VX_forwarding.v

@@ -0,0 +1,155 @@
+
+`include "VX_define.v"
+
+module VX_forwarding (
+		// INFO FROM DECODE
+		input wire[4:0]  in_decode_src1,
+		input wire[4:0]  in_decode_src2,
+		input wire[11:0] in_decode_csr_address, 
+
+		// INFO FROM EXE
+		input wire[4:0]  in_execute_dest,
+		input wire[1:0]  in_execute_wb,
+		input wire[31:0] in_execute_alu_result,
+		input wire[31:0] in_execute_PC_next,
+		input wire       in_execute_is_csr,
+		input wire[11:0] in_execute_csr_address,
+
+		// INFO FROM MEM
+		input wire[4:0]  in_memory_dest,
+		input wire[1:0]  in_memory_wb,
+		input wire[31:0] in_memory_alu_result,
+		input wire[31:0] in_memory_mem_data,
+		input wire[31:0] in_memory_PC_next,
+		input wire       in_memory_is_csr,
+		input wire[11:0] in_memory_csr_address,
+		input wire[31:0] in_memory_csr_result,
+
+		// INFO FROM WB
+		input wire[4:0]  in_writeback_dest,
+		input wire[1:0]  in_writeback_wb,
+		input wire[31:0] in_writeback_alu_result,
+		input wire[31:0] in_writeback_mem_data,
+		input wire[31:0] in_writeback_PC_next,
+
+		// OUT SIGNALS
+		output wire       out_src1_fwd,
+		output wire       out_src2_fwd,
+		output wire       out_csr_fwd,
+		output wire[31:0] out_src1_fwd_data,
+		output wire[31:0] out_src2_fwd_data,
+		output wire[31:0] out_csr_fwd_data,
+		output wire       out_fwd_stall
+	);
+
+
+
+		wire exe_mem_read;
+		wire mem_mem_read;
+		wire wb_mem_read ;
+		wire exe_jal;
+		wire mem_jal;
+		wire wb_jal ;
+		wire exe_csr;
+		wire mem_csr;
+		wire src1_exe_fwd;
+		wire src1_mem_fwd;
+		wire src1_wb_fwd;
+		wire src2_exe_fwd;
+		wire src2_mem_fwd;
+		wire src2_wb_fwd;
+		wire csr_exe_fwd;
+		wire csr_mem_fwd;
+
+
+		assign exe_mem_read = (in_execute_wb   == `WB_MEM);
+		assign mem_mem_read = (in_memory_wb    == `WB_MEM);
+		assign wb_mem_read  = (in_writeback_wb == `WB_MEM);
+
+		assign exe_jal = (in_execute_wb   == `WB_JAL);
+		assign mem_jal = (in_memory_wb    == `WB_JAL);
+		assign wb_jal  = (in_writeback_wb == `WB_JAL);
+
+		assign exe_csr = (in_execute_is_csr == 1'b1);
+		assign mem_csr = (in_memory_is_csr == 1'b1);
+
+
+		// SRC1
+		assign src1_exe_fwd = ((in_decode_src1 == in_execute_dest) && 
+								(in_decode_src1 != `ZERO_REG) &&
+			                     (in_execute_wb != `NO_WB));
+
+		assign src1_mem_fwd = ((in_decode_src1 == in_memory_dest) &&
+							    (in_decode_src1 != `ZERO_REG) &&
+			                      (in_memory_wb != `NO_WB) &&
+			                      (!src1_exe_fwd));
+
+		assign src1_wb_fwd = ((in_decode_src1 == in_writeback_dest) &&
+							   (in_decode_src1 != `ZERO_REG) &&
+			                  (in_writeback_wb != `NO_WB) &&
+			                      (!src1_exe_fwd) &&
+			                      (!src1_mem_fwd));
+
+
+		assign out_src1_fwd  = src1_exe_fwd || src1_mem_fwd || src1_wb_fwd; // COMMENT
+
+
+
+
+
+		// SRC2
+		assign src2_exe_fwd = ((in_decode_src2 == in_execute_dest) && 
+								(in_decode_src2 != `ZERO_REG) &&
+			                     (in_execute_wb != `NO_WB));
+
+		assign src2_mem_fwd = ((in_decode_src2 == in_memory_dest) &&
+								(in_decode_src2 != `ZERO_REG) &&
+			                      (in_memory_wb != `NO_WB) &&
+			                      (!src2_exe_fwd));
+
+		assign src2_wb_fwd = ((in_decode_src2 == in_writeback_dest) &&
+							   (in_decode_src2 != `ZERO_REG) &&
+			                  (in_writeback_wb != `NO_WB) &&
+			                      (!src2_exe_fwd) &&
+			                      (!src2_mem_fwd));
+
+
+		assign out_src2_fwd  = src2_exe_fwd || src2_mem_fwd || src2_wb_fwd; // COMMENT
+
+
+
+		// CSR
+		assign csr_exe_fwd = (in_decode_csr_address == in_execute_csr_address) && exe_csr;
+		assign csr_mem_fwd = (in_decode_csr_address == in_memory_csr_address)  && mem_csr && !csr_exe_fwd;
+
+		assign out_csr_fwd      = csr_exe_fwd || csr_mem_fwd; // COMMENT
+
+
+
+		assign out_fwd_stall = ((src1_exe_fwd || src2_exe_fwd) && exe_mem_read) ? `STALL : `NO_STALL; 
+
+
+		assign out_src1_fwd_data = src1_exe_fwd ? ((exe_jal) ? in_execute_PC_next : in_execute_alu_result) :
+			                          (src1_mem_fwd) ? ((mem_jal) ? in_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) :
+									    ( src1_wb_fwd ) ?  (wb_jal ? in_writeback_PC_next : (wb_mem_read ?  in_writeback_mem_data : in_writeback_alu_result)) :
+										 	32'hdeadbeef; // COMMENT
+
+		assign out_src2_fwd_data = src2_exe_fwd ? ((exe_jal) ? in_execute_PC_next : in_execute_alu_result) :
+			                        (src2_mem_fwd) ? ((mem_jal) ? in_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) :
+									    ( src2_wb_fwd ) ?  (wb_jal ? in_writeback_PC_next : (wb_mem_read ?  in_writeback_mem_data : in_writeback_alu_result)) :
+										 	32'hdeadbeef; // COMMENT
+		
+		assign out_csr_fwd_data = csr_exe_fwd ? in_execute_alu_result :
+									 csr_mem_fwd ? in_memory_csr_result :
+									 	    	32'hdeadbeef; // COMMENT
+
+
+
+endmodule // VX_forwarding
+
+
+
+
+
+
+

rtl/VX_m_w_reg.v

@@ -0,0 +1,78 @@
+
+
+`include "VX_define.v"
+
+module VX_m_w_reg (
+		input wire        clk,
+		input wire[31:0]  in_alu_result,
+		input wire[31:0]  in_mem_result, // NEW
+		input wire[4:0]   in_rd,
+		input wire[1:0]   in_wb,
+		input wire[4:0]   in_rs1,
+		input wire[4:0]   in_rs2,
+		input wire[31:0]  in_PC_next,
+		input wire        in_freeze,
+		input wire        in_valid,
+
+		output wire[31:0] out_alu_result,
+		output wire[31:0] out_mem_result, // NEW
+		output wire[4:0]  out_rd,
+		output wire[1:0]  out_wb,
+		output wire[4:0]  out_rs1,
+		output wire[4:0]  out_rs2,
+		output wire[31:0] out_PC_next,
+		output wire       out_valid
+	);
+
+
+
+		reg[31:0] alu_result;
+		reg[31:0] mem_result;
+		reg[4:0]  rd;
+		reg[4:0]  rs1;
+		reg[4:0]  rs2;
+		reg[1:0]  wb;
+		reg[31:0] PC_next;
+		reg       valid;
+
+
+		initial begin
+			alu_result  = 0;
+			mem_result  = 0;
+			rd          = 0;
+			rs1         = 0;
+			rs2         = 0;
+			wb          = 0;
+			PC_next     = 0;
+			valid       = 0;
+		end
+
+		assign out_alu_result  = alu_result;
+		assign out_mem_result  = mem_result;
+		assign out_rd          = rd;
+		assign out_rs1         = rs1;
+		assign out_rs2         = rs2;
+		assign out_wb          = wb;
+		assign out_PC_next     = PC_next;
+		assign out_valid       = valid;
+		
+
+		always @(posedge clk) begin
+			if(in_freeze == 1'b0) begin
+				alu_result   <= in_alu_result;
+				mem_result   <= in_mem_result;
+				rd           <= in_rd;
+				rs1          <= in_rs1;
+				rs2          <= in_rs2;
+				wb           <= in_wb;
+				PC_next      <= in_PC_next;
+				valid        <= in_valid;
+			end
+		end
+
+
+
+endmodule // VX_m_w_reg
+
+
+

rtl/VX_memory.v

@@ -0,0 +1,77 @@
+
+`include "VX_define.v"
+
+
+module VX_memory (
+		input wire[31:0]  in_alu_result,
+		input wire[2:0]   in_mem_read, 
+		input wire[2:0]   in_mem_write,
+		input wire[4:0]   in_rd,
+		input wire[1:0]   in_wb,
+		input wire[4:0]   in_rs1,
+		input wire[4:0]   in_rs2,
+		input wire[31:0]  in_rd2,
+		input wire[31:0]  in_PC_next,
+		input wire[31:0]  in_curr_PC,
+		input wire[31:0]  in_branch_offset,
+		input wire[2:0]   in_branch_type, 
+		input wire        in_valid,
+		input wire[31:0]  in_cache_driver_out_data,
+
+		output wire[31:0] out_alu_result,
+		output wire[31:0] out_mem_result,
+		output wire[4:0]  out_rd,
+		output wire[1:0]  out_wb,
+		output wire[4:0]  out_rs1,
+		output wire[4:0]  out_rs2,
+		output reg        out_branch_dir,
+		output wire[31:0] out_branch_dest,
+		output wire       out_delay,
+		output wire[31:0] out_PC_next,
+		output wire       out_valid,
+		output wire[31:0] out_cache_driver_in_address,
+		output wire[2:0]  out_cache_driver_in_mem_read,
+		output wire[2:0]  out_cache_driver_in_mem_write,
+		output wire[31:0] out_cache_driver_in_data 
+	);	
+
+		assign out_delay = 1'b0;
+
+		assign out_cache_driver_in_address   = in_alu_result;
+		assign out_cache_driver_in_mem_read  = in_mem_read;
+		assign out_cache_driver_in_mem_write = in_mem_write;
+		assign out_cache_driver_in_data      = in_rd2;
+
+
+		assign out_mem_result = in_cache_driver_out_data;
+		assign out_alu_result = in_alu_result;
+		assign out_rd = in_rd;
+		assign out_wb = in_wb;
+		assign out_rs1 = in_rs1;
+		assign out_rs2 = in_rs2;
+		assign out_PC_next = in_PC_next;
+
+		assign out_valid = in_valid;
+
+
+		assign out_branch_dest = $signed(in_curr_PC) + ($signed(in_branch_offset) << 1);
+
+
+		always @(*) begin
+			case(in_branch_type)
+				`BEQ:  out_branch_dir = (in_alu_result == 0)     ? `TAKEN     : `NOT_TAKEN;
+				`BNE:  out_branch_dir = (in_alu_result == 0)     ? `NOT_TAKEN : `TAKEN;
+				`BLT:  out_branch_dir = (in_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN;
+				`BGT:  out_branch_dir = (in_alu_result[31] == 0) ? `TAKEN     : `NOT_TAKEN;
+				`BLTU: out_branch_dir = (in_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN;
+				`BGTU: out_branch_dir = (in_alu_result[31] == 0) ? `TAKEN     : `NOT_TAKEN;
+				`NO_BRANCH: out_branch_dir = `NOT_TAKEN;
+				default:    out_branch_dir = `NOT_TAKEN;
+			endcase // in_branch_type
+		end
+
+
+
+endmodule // Memory
+
+

rtl/VX_writeback.v

@@ -0,0 +1,33 @@
+
+`include "VX_define.v"
+
+
+module VX_writeback (
+		input wire[31:0] in_alu_result,
+		input wire[31:0] in_mem_result,
+		input wire[4:0]  in_rd,
+		input wire[1:0]  in_wb,
+		input wire[31:0] in_PC_next,
+
+		output wire[31:0] out_write_data,
+		output wire[4:0] out_rd,
+		output wire[1:0] out_wb
+	);
+
+		wire is_jal;
+		wire uses_alu;
+
+
+		assign is_jal   = in_wb == `WB_JAL;
+		assign uses_alu = in_wb == `WB_ALU;
+
+		assign out_write_data = is_jal ? in_PC_next :
+										uses_alu ? in_alu_result :
+													in_mem_result;
+
+
+		assign out_rd = in_rd;
+		assign out_wb = in_wb;
+
+
+endmodule // VX_writeback

rtl/obj_dir/VVX_decode.cpp

@@ -1,975 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Design implementation internals
-// See VVX_decode.h for the primary calling header
-
-#include "VVX_decode.h"
-#include "VVX_decode__Syms.h"
-
-
-//--------------------
-// STATIC VARIABLES
-
-
-//--------------------
-
-VL_CTOR_IMP(VVX_decode) {
-    VVX_decode__Syms* __restrict vlSymsp = __VlSymsp = new VVX_decode__Syms(this, name());
-    VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Reset internal values
-    
-    // Reset structure values
-    _ctor_var_reset();
-}
-
-void VVX_decode::__Vconfigure(VVX_decode__Syms* vlSymsp, bool first) {
-    if (0 && first) {}  // Prevent unused
-    this->__VlSymsp = vlSymsp;
-}
-
-VVX_decode::~VVX_decode() {
-    delete __VlSymsp; __VlSymsp=NULL;
-}
-
-//--------------------
-
-
-void VVX_decode::eval() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_decode::eval\n"); );
-    VVX_decode__Syms* __restrict vlSymsp = this->__VlSymsp;  // Setup global symbol table
-    VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-#ifdef VL_DEBUG
-    // Debug assertions
-    _eval_debug_assertions();
-#endif // VL_DEBUG
-    // Initialize
-    if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
-    // Evaluate till stable
-    int __VclockLoop = 0;
-    QData __Vchange = 1;
-    do {
-	VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
-	_eval(vlSymsp);
-	if (VL_UNLIKELY(++__VclockLoop > 100)) {
-	    // About to fail, so enable debug to see what's not settling.
-	    // Note you must run make with OPT=-DVL_DEBUG for debug prints.
-	    int __Vsaved_debug = Verilated::debug();
-	    Verilated::debug(1);
-	    __Vchange = _change_request(vlSymsp);
-	    Verilated::debug(__Vsaved_debug);
-	    VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
-	} else {
-	    __Vchange = _change_request(vlSymsp);
-	}
-    } while (VL_UNLIKELY(__Vchange));
-}
-
-void VVX_decode::_eval_initial_loop(VVX_decode__Syms* __restrict vlSymsp) {
-    vlSymsp->__Vm_didInit = true;
-    _eval_initial(vlSymsp);
-    // Evaluate till stable
-    int __VclockLoop = 0;
-    QData __Vchange = 1;
-    do {
-	_eval_settle(vlSymsp);
-	_eval(vlSymsp);
-	if (VL_UNLIKELY(++__VclockLoop > 100)) {
-	    // About to fail, so enable debug to see what's not settling.
-	    // Note you must run make with OPT=-DVL_DEBUG for debug prints.
-	    int __Vsaved_debug = Verilated::debug();
-	    Verilated::debug(1);
-	    __Vchange = _change_request(vlSymsp);
-	    Verilated::debug(__Vsaved_debug);
-	    VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
-	} else {
-	    __Vchange = _change_request(vlSymsp);
-	}
-    } while (VL_UNLIKELY(__Vchange));
-}
-
-//--------------------
-// Internal Methods
-
-VL_INLINE_OPT void VVX_decode::_combo__TOP__1(VVX_decode__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_decode::_combo__TOP__1\n"); );
-    VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    vlTOPp->out_PC_next = ((IData)(4U) + vlTOPp->in_curr_PC);
-    vlTOPp->out_mem_read = (7U & ((3U == (0x7fU & vlTOPp->in_instruction))
-				   ? (vlTOPp->in_instruction 
-				      >> 0xcU) : 7U));
-    vlTOPp->out_mem_write = (7U & ((0x23U == (0x7fU 
-					      & vlTOPp->in_instruction))
-				    ? (vlTOPp->in_instruction 
-				       >> 0xcU) : 7U));
-    // ALWAYS at VX_decode.v:247
-    vlTOPp->out_jal = ((0x6fU == (0x7fU & vlTOPp->in_instruction)) 
-		       | ((0x67U == (0x7fU & vlTOPp->in_instruction)) 
-			  | ((0x73U == (0x7fU & vlTOPp->in_instruction)) 
-			     & ((0U == (7U & (vlTOPp->in_instruction 
-					      >> 0xcU))) 
-				& (2U > (0xfffU & (vlTOPp->in_instruction 
-						   >> 0x14U)))))));
-    vlTOPp->out_csr_address = (0xfffU & (((0U != (7U 
-						  & (vlTOPp->in_instruction 
-						     >> 0xcU))) 
-					  & (2U <= 
-					     (0xfffU 
-					      & (vlTOPp->in_instruction 
-						 >> 0x14U))))
-					  ? (vlTOPp->in_instruction 
-					     >> 0x14U)
-					  : 0x55U));
-    // ALWAYS at VX_decode.v:306
-    vlTOPp->out_branch_stall = ((0x63U == (0x7fU & vlTOPp->in_instruction)) 
-				| ((0x6fU == (0x7fU 
-					      & vlTOPp->in_instruction)) 
-				   | (0x67U == (0x7fU 
-						& vlTOPp->in_instruction))));
-    vlTOPp->out_rd = (0x1fU & (vlTOPp->in_instruction 
-			       >> 7U));
-    // ALWAYS at VX_decode.v:306
-    vlTOPp->out_branch_type = ((0x63U == (0x7fU & vlTOPp->in_instruction))
-			        ? ((0x4000U & vlTOPp->in_instruction)
-				    ? ((0x2000U & vlTOPp->in_instruction)
-				        ? ((0x1000U 
-					    & vlTOPp->in_instruction)
-					    ? 6U : 5U)
-				        : ((0x1000U 
-					    & vlTOPp->in_instruction)
-					    ? 4U : 3U))
-				    : ((0x2000U & vlTOPp->in_instruction)
-				        ? 0U : ((0x1000U 
-						 & vlTOPp->in_instruction)
-						 ? 2U
-						 : 1U)))
-			        : 0U);
-    vlTOPp->VX_decode__DOT__is_itype = ((0x13U == (0x7fU 
-						   & vlTOPp->in_instruction)) 
-					| (3U == (0x7fU 
-						  & vlTOPp->in_instruction)));
-    vlTOPp->VX_decode__DOT__is_csr = ((0x73U == (0x7fU 
-						 & vlTOPp->in_instruction)) 
-				      & (0U != (7U 
-						& (vlTOPp->in_instruction 
-						   >> 0xcU))));
-    vlTOPp->out_rs1 = (0x1fU & (vlTOPp->in_instruction 
-				>> 0xfU));
-    vlTOPp->out_rs2 = (0x1fU & (vlTOPp->in_instruction 
-				>> 0x14U));
-    vlTOPp->out_rs2_src = (1U & (((IData)(vlTOPp->VX_decode__DOT__is_itype) 
-				  | (0x23U == (0x7fU 
-					       & vlTOPp->in_instruction)))
-				  ? 1U : 0U));
-    vlTOPp->out_is_csr = vlTOPp->VX_decode__DOT__is_csr;
-    vlTOPp->out_wb = ((((0x6fU == (0x7fU & vlTOPp->in_instruction)) 
-			| (0x67U == (0x7fU & vlTOPp->in_instruction))) 
-		       | ((0x73U == (0x7fU & vlTOPp->in_instruction)) 
-			  & (0U == (7U & (vlTOPp->in_instruction 
-					  >> 0xcU)))))
-		       ? 3U : ((3U == (0x7fU & vlTOPp->in_instruction))
-			        ? 2U : ((((((IData)(vlTOPp->VX_decode__DOT__is_itype) 
-					    | (0x33U 
-					       == (0x7fU 
-						   & vlTOPp->in_instruction))) 
-					   | (0x37U 
-					      == (0x7fU 
-						  & vlTOPp->in_instruction))) 
-					  | (0x17U 
-					     == (0x7fU 
-						 & vlTOPp->in_instruction))) 
-					 | (IData)(vlTOPp->VX_decode__DOT__is_csr))
-					 ? 1U : 0U)));
-    vlTOPp->out_alu_op = ((0x63U == (0x7fU & vlTOPp->in_instruction))
-			   ? ((5U > (IData)(vlTOPp->out_branch_type))
-			       ? 1U : 0xaU) : ((0x37U 
-						== 
-						(0x7fU 
-						 & vlTOPp->in_instruction))
-					        ? 0xbU
-					        : (
-						   (0x17U 
-						    == 
-						    (0x7fU 
-						     & vlTOPp->in_instruction))
-						    ? 0xcU
-						    : 
-						   ((IData)(vlTOPp->VX_decode__DOT__is_csr)
-						     ? 
-						    ((1U 
-						      == 
-						      (3U 
-						       & (vlTOPp->in_instruction 
-							  >> 0xcU)))
-						      ? 0xdU
-						      : 
-						     ((2U 
-						       == 
-						       (3U 
-							& (vlTOPp->in_instruction 
-							   >> 0xcU)))
-						       ? 0xeU
-						       : 0xfU))
-						     : 
-						    (((0x23U 
-						       == 
-						       (0x7fU 
-							& vlTOPp->in_instruction)) 
-						      | (3U 
-							 == 
-							 (0x7fU 
-							  & vlTOPp->in_instruction)))
-						      ? 0U
-						      : 
-						     ((0x4000U 
-						       & vlTOPp->in_instruction)
-						       ? 
-						      ((0x2000U 
-							& vlTOPp->in_instruction)
-						        ? 
-						       ((0x1000U 
-							 & vlTOPp->in_instruction)
-							 ? 9U
-							 : 8U)
-						        : 
-						       ((0x1000U 
-							 & vlTOPp->in_instruction)
-							 ? 
-							((0U 
-							  == 
-							  (0x7fU 
-							   & (vlTOPp->in_instruction 
-							      >> 0x19U)))
-							  ? 6U
-							  : 7U)
-							 : 5U))
-						       : 
-						      ((0x2000U 
-							& vlTOPp->in_instruction)
-						        ? 
-						       ((0x1000U 
-							 & vlTOPp->in_instruction)
-							 ? 4U
-							 : 3U)
-						        : 
-						       ((0x1000U 
-							 & vlTOPp->in_instruction)
-							 ? 2U
-							 : 
-							((0x13U 
-							  == 
-							  (0x7fU 
-							   & vlTOPp->in_instruction))
-							  ? 0U
-							  : 
-							 ((0U 
-							   == 
-							   (0x7fU 
-							    & (vlTOPp->in_instruction 
-							       >> 0x19U)))
-							   ? 0U
-							   : 1U))))))))));
-    // ALWAYS at VX_decode.v:201
-    vlTOPp->out_upper_immed = ((0x37U == (0x7fU & vlTOPp->in_instruction))
-			        ? ((0xfe000U & (vlTOPp->in_instruction 
-						>> 0xcU)) 
-				   | (((IData)(vlTOPp->out_rs2) 
-				       << 8U) | (((IData)(vlTOPp->out_rs1) 
-						  << 3U) 
-						 | (7U 
-						    & (vlTOPp->in_instruction 
-						       >> 0xcU)))))
-			        : ((0x17U == (0x7fU 
-					      & vlTOPp->in_instruction))
-				    ? ((0xfe000U & 
-					(vlTOPp->in_instruction 
-					 >> 0xcU)) 
-				       | (((IData)(vlTOPp->out_rs2) 
-					   << 8U) | 
-					  (((IData)(vlTOPp->out_rs1) 
-					    << 3U) 
-					   | (7U & 
-					      (vlTOPp->in_instruction 
-					       >> 0xcU)))))
-				    : 0U));
-    vlTOPp->VX_decode__DOT__jalr_immed = ((0xfe0U & 
-					   (vlTOPp->in_instruction 
-					    >> 0x14U)) 
-					  | (IData)(vlTOPp->out_rs2));
-    vlTOPp->VX_decode__DOT__alu_tempp = (0xfffU & (
-						   ((1U 
-						     == 
-						     (7U 
-						      & (vlTOPp->in_instruction 
-							 >> 0xcU))) 
-						    | (5U 
-						       == 
-						       (7U 
-							& (vlTOPp->in_instruction 
-							   >> 0xcU))))
-						    ? (IData)(vlTOPp->out_rs2)
-						    : 
-						   (vlTOPp->in_instruction 
-						    >> 0x14U)));
-    // ALWAYS at VX_decode.v:247
-    vlTOPp->out_jal_offset = ((0x6fU == (0x7fU & vlTOPp->in_instruction))
-			       ? ((0xffe00000U & (VL_NEGATE_I((IData)(
-								      (1U 
-								       & (vlTOPp->in_instruction 
-									  >> 0x1fU)))) 
-						  << 0x15U)) 
-				  | ((0x100000U & (vlTOPp->in_instruction 
-						   >> 0xbU)) 
-				     | ((0xff000U & vlTOPp->in_instruction) 
-					| ((0x800U 
-					    & (vlTOPp->in_instruction 
-					       >> 9U)) 
-					   | (0x7feU 
-					      & (vlTOPp->in_instruction 
-						 >> 0x14U))))))
-			       : ((0x67U == (0x7fU 
-					     & vlTOPp->in_instruction))
-				   ? ((0xfffff000U 
-				       & (VL_NEGATE_I((IData)(
-							      (1U 
-							       & ((IData)(vlTOPp->VX_decode__DOT__jalr_immed) 
-								  >> 0xbU)))) 
-					  << 0xcU)) 
-				      | (IData)(vlTOPp->VX_decode__DOT__jalr_immed))
-				   : ((0x73U == (0x7fU 
-						 & vlTOPp->in_instruction))
-				       ? (((0U == (7U 
-						   & (vlTOPp->in_instruction 
-						      >> 0xcU))) 
-					   & (2U > 
-					      (0xfffU 
-					       & (vlTOPp->in_instruction 
-						  >> 0x14U))))
-					   ? 0xb0000000U
-					   : 0xdeadbeefU)
-				       : 0xdeadbeefU)));
-    // ALWAYS at VX_decode.v:295
-    vlTOPp->out_itype_immed = ((0x40U & vlTOPp->in_instruction)
-			        ? ((0x20U & vlTOPp->in_instruction)
-				    ? ((0x10U & vlTOPp->in_instruction)
-				        ? 0xdeadbeefU
-				        : ((8U & vlTOPp->in_instruction)
-					    ? 0xdeadbeefU
-					    : ((4U 
-						& vlTOPp->in_instruction)
-					        ? 0xdeadbeefU
-					        : (
-						   (2U 
-						    & vlTOPp->in_instruction)
-						    ? 
-						   ((1U 
-						     & vlTOPp->in_instruction)
-						     ? 
-						    ((0xfffff000U 
-						      & (VL_NEGATE_I((IData)(
-									     (1U 
-									      & (vlTOPp->in_instruction 
-										>> 0x1fU)))) 
-							 << 0xcU)) 
-						     | ((0x800U 
-							 & (vlTOPp->in_instruction 
-							    >> 0x14U)) 
-							| ((0x400U 
-							    & (vlTOPp->in_instruction 
-							       << 3U)) 
-							   | ((0x3f0U 
-							       & (vlTOPp->in_instruction 
-								  >> 0x15U)) 
-							      | (0xfU 
-								 & (vlTOPp->in_instruction 
-								    >> 8U))))))
-						     : 0xdeadbeefU)
-						    : 0xdeadbeefU))))
-				    : 0xdeadbeefU) : 
-			       ((0x20U & vlTOPp->in_instruction)
-				 ? ((0x10U & vlTOPp->in_instruction)
-				     ? 0xdeadbeefU : 
-				    ((8U & vlTOPp->in_instruction)
-				      ? 0xdeadbeefU
-				      : ((4U & vlTOPp->in_instruction)
-					  ? 0xdeadbeefU
-					  : ((2U & vlTOPp->in_instruction)
-					      ? ((1U 
-						  & vlTOPp->in_instruction)
-						  ? 
-						 ((0xfffff000U 
-						   & (VL_NEGATE_I((IData)(
-									  (1U 
-									   & (vlTOPp->in_instruction 
-									      >> 0x1fU)))) 
-						      << 0xcU)) 
-						  | ((0xfe0U 
-						      & (vlTOPp->in_instruction 
-							 >> 0x14U)) 
-						     | (IData)(vlTOPp->out_rd)))
-						  : 0xdeadbeefU)
-					      : 0xdeadbeefU))))
-				 : ((0x10U & vlTOPp->in_instruction)
-				     ? ((8U & vlTOPp->in_instruction)
-					 ? 0xdeadbeefU
-					 : ((4U & vlTOPp->in_instruction)
-					     ? 0xdeadbeefU
-					     : ((2U 
-						 & vlTOPp->in_instruction)
-						 ? 
-						((1U 
-						  & vlTOPp->in_instruction)
-						  ? 
-						 ((0xfffff000U 
-						   & (VL_NEGATE_I((IData)(
-									  (1U 
-									   & ((IData)(vlTOPp->VX_decode__DOT__alu_tempp) 
-									      >> 0xbU)))) 
-						      << 0xcU)) 
-						  | (IData)(vlTOPp->VX_decode__DOT__alu_tempp))
-						  : 0xdeadbeefU)
-						 : 0xdeadbeefU)))
-				     : ((8U & vlTOPp->in_instruction)
-					 ? 0xdeadbeefU
-					 : ((4U & vlTOPp->in_instruction)
-					     ? 0xdeadbeefU
-					     : ((2U 
-						 & vlTOPp->in_instruction)
-						 ? 
-						((1U 
-						  & vlTOPp->in_instruction)
-						  ? 
-						 ((0xfffff000U 
-						   & (VL_NEGATE_I((IData)(
-									  (1U 
-									   & (vlTOPp->in_instruction 
-									      >> 0x1fU)))) 
-						      << 0xcU)) 
-						  | (0xfffU 
-						     & (vlTOPp->in_instruction 
-							>> 0x14U)))
-						  : 0xdeadbeefU)
-						 : 0xdeadbeefU))))));
-}
-
-void VVX_decode::_settle__TOP__2(VVX_decode__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_decode::_settle__TOP__2\n"); );
-    VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    vlTOPp->out_PC_next = ((IData)(4U) + vlTOPp->in_curr_PC);
-    vlTOPp->out_mem_read = (7U & ((3U == (0x7fU & vlTOPp->in_instruction))
-				   ? (vlTOPp->in_instruction 
-				      >> 0xcU) : 7U));
-    vlTOPp->out_mem_write = (7U & ((0x23U == (0x7fU 
-					      & vlTOPp->in_instruction))
-				    ? (vlTOPp->in_instruction 
-				       >> 0xcU) : 7U));
-    // ALWAYS at VX_decode.v:247
-    vlTOPp->out_jal = ((0x6fU == (0x7fU & vlTOPp->in_instruction)) 
-		       | ((0x67U == (0x7fU & vlTOPp->in_instruction)) 
-			  | ((0x73U == (0x7fU & vlTOPp->in_instruction)) 
-			     & ((0U == (7U & (vlTOPp->in_instruction 
-					      >> 0xcU))) 
-				& (2U > (0xfffU & (vlTOPp->in_instruction 
-						   >> 0x14U)))))));
-    vlTOPp->out_csr_address = (0xfffU & (((0U != (7U 
-						  & (vlTOPp->in_instruction 
-						     >> 0xcU))) 
-					  & (2U <= 
-					     (0xfffU 
-					      & (vlTOPp->in_instruction 
-						 >> 0x14U))))
-					  ? (vlTOPp->in_instruction 
-					     >> 0x14U)
-					  : 0x55U));
-    // ALWAYS at VX_decode.v:306
-    vlTOPp->out_branch_stall = ((0x63U == (0x7fU & vlTOPp->in_instruction)) 
-				| ((0x6fU == (0x7fU 
-					      & vlTOPp->in_instruction)) 
-				   | (0x67U == (0x7fU 
-						& vlTOPp->in_instruction))));
-    vlTOPp->out_rd = (0x1fU & (vlTOPp->in_instruction 
-			       >> 7U));
-    // ALWAYS at VX_decode.v:306
-    vlTOPp->out_branch_type = ((0x63U == (0x7fU & vlTOPp->in_instruction))
-			        ? ((0x4000U & vlTOPp->in_instruction)
-				    ? ((0x2000U & vlTOPp->in_instruction)
-				        ? ((0x1000U 
-					    & vlTOPp->in_instruction)
-					    ? 6U : 5U)
-				        : ((0x1000U 
-					    & vlTOPp->in_instruction)
-					    ? 4U : 3U))
-				    : ((0x2000U & vlTOPp->in_instruction)
-				        ? 0U : ((0x1000U 
-						 & vlTOPp->in_instruction)
-						 ? 2U
-						 : 1U)))
-			        : 0U);
-    vlTOPp->VX_decode__DOT__is_itype = ((0x13U == (0x7fU 
-						   & vlTOPp->in_instruction)) 
-					| (3U == (0x7fU 
-						  & vlTOPp->in_instruction)));
-    vlTOPp->VX_decode__DOT__is_csr = ((0x73U == (0x7fU 
-						 & vlTOPp->in_instruction)) 
-				      & (0U != (7U 
-						& (vlTOPp->in_instruction 
-						   >> 0xcU))));
-    vlTOPp->out_rs1 = (0x1fU & (vlTOPp->in_instruction 
-				>> 0xfU));
-    vlTOPp->out_rs2 = (0x1fU & (vlTOPp->in_instruction 
-				>> 0x14U));
-    vlTOPp->out_rs2_src = (1U & (((IData)(vlTOPp->VX_decode__DOT__is_itype) 
-				  | (0x23U == (0x7fU 
-					       & vlTOPp->in_instruction)))
-				  ? 1U : 0U));
-    vlTOPp->out_is_csr = vlTOPp->VX_decode__DOT__is_csr;
-    vlTOPp->out_wb = ((((0x6fU == (0x7fU & vlTOPp->in_instruction)) 
-			| (0x67U == (0x7fU & vlTOPp->in_instruction))) 
-		       | ((0x73U == (0x7fU & vlTOPp->in_instruction)) 
-			  & (0U == (7U & (vlTOPp->in_instruction 
-					  >> 0xcU)))))
-		       ? 3U : ((3U == (0x7fU & vlTOPp->in_instruction))
-			        ? 2U : ((((((IData)(vlTOPp->VX_decode__DOT__is_itype) 
-					    | (0x33U 
-					       == (0x7fU 
-						   & vlTOPp->in_instruction))) 
-					   | (0x37U 
-					      == (0x7fU 
-						  & vlTOPp->in_instruction))) 
-					  | (0x17U 
-					     == (0x7fU 
-						 & vlTOPp->in_instruction))) 
-					 | (IData)(vlTOPp->VX_decode__DOT__is_csr))
-					 ? 1U : 0U)));
-    vlTOPp->out_alu_op = ((0x63U == (0x7fU & vlTOPp->in_instruction))
-			   ? ((5U > (IData)(vlTOPp->out_branch_type))
-			       ? 1U : 0xaU) : ((0x37U 
-						== 
-						(0x7fU 
-						 & vlTOPp->in_instruction))
-					        ? 0xbU
-					        : (
-						   (0x17U 
-						    == 
-						    (0x7fU 
-						     & vlTOPp->in_instruction))
-						    ? 0xcU
-						    : 
-						   ((IData)(vlTOPp->VX_decode__DOT__is_csr)
-						     ? 
-						    ((1U 
-						      == 
-						      (3U 
-						       & (vlTOPp->in_instruction 
-							  >> 0xcU)))
-						      ? 0xdU
-						      : 
-						     ((2U 
-						       == 
-						       (3U 
-							& (vlTOPp->in_instruction 
-							   >> 0xcU)))
-						       ? 0xeU
-						       : 0xfU))
-						     : 
-						    (((0x23U 
-						       == 
-						       (0x7fU 
-							& vlTOPp->in_instruction)) 
-						      | (3U 
-							 == 
-							 (0x7fU 
-							  & vlTOPp->in_instruction)))
-						      ? 0U
-						      : 
-						     ((0x4000U 
-						       & vlTOPp->in_instruction)
-						       ? 
-						      ((0x2000U 
-							& vlTOPp->in_instruction)
-						        ? 
-						       ((0x1000U 
-							 & vlTOPp->in_instruction)
-							 ? 9U
-							 : 8U)
-						        : 
-						       ((0x1000U 
-							 & vlTOPp->in_instruction)
-							 ? 
-							((0U 
-							  == 
-							  (0x7fU 
-							   & (vlTOPp->in_instruction 
-							      >> 0x19U)))
-							  ? 6U
-							  : 7U)
-							 : 5U))
-						       : 
-						      ((0x2000U 
-							& vlTOPp->in_instruction)
-						        ? 
-						       ((0x1000U 
-							 & vlTOPp->in_instruction)
-							 ? 4U
-							 : 3U)
-						        : 
-						       ((0x1000U 
-							 & vlTOPp->in_instruction)
-							 ? 2U
-							 : 
-							((0x13U 
-							  == 
-							  (0x7fU 
-							   & vlTOPp->in_instruction))
-							  ? 0U
-							  : 
-							 ((0U 
-							   == 
-							   (0x7fU 
-							    & (vlTOPp->in_instruction 
-							       >> 0x19U)))
-							   ? 0U
-							   : 1U))))))))));
-    vlTOPp->out_rd1 = ((0x6fU == (0x7fU & vlTOPp->in_instruction))
-		        ? vlTOPp->in_curr_PC : ((IData)(vlTOPp->in_src1_fwd)
-						 ? vlTOPp->in_src1_fwd_data
-						 : 
-						vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers
-						[vlTOPp->out_rs1]));
-    // ALWAYS at VX_decode.v:201
-    vlTOPp->out_upper_immed = ((0x37U == (0x7fU & vlTOPp->in_instruction))
-			        ? ((0xfe000U & (vlTOPp->in_instruction 
-						>> 0xcU)) 
-				   | (((IData)(vlTOPp->out_rs2) 
-				       << 8U) | (((IData)(vlTOPp->out_rs1) 
-						  << 3U) 
-						 | (7U 
-						    & (vlTOPp->in_instruction 
-						       >> 0xcU)))))
-			        : ((0x17U == (0x7fU 
-					      & vlTOPp->in_instruction))
-				    ? ((0xfe000U & 
-					(vlTOPp->in_instruction 
-					 >> 0xcU)) 
-				       | (((IData)(vlTOPp->out_rs2) 
-					   << 8U) | 
-					  (((IData)(vlTOPp->out_rs1) 
-					    << 3U) 
-					   | (7U & 
-					      (vlTOPp->in_instruction 
-					       >> 0xcU)))))
-				    : 0U));
-    vlTOPp->VX_decode__DOT__jalr_immed = ((0xfe0U & 
-					   (vlTOPp->in_instruction 
-					    >> 0x14U)) 
-					  | (IData)(vlTOPp->out_rs2));
-    vlTOPp->VX_decode__DOT__alu_tempp = (0xfffU & (
-						   ((1U 
-						     == 
-						     (7U 
-						      & (vlTOPp->in_instruction 
-							 >> 0xcU))) 
-						    | (5U 
-						       == 
-						       (7U 
-							& (vlTOPp->in_instruction 
-							   >> 0xcU))))
-						    ? (IData)(vlTOPp->out_rs2)
-						    : 
-						   (vlTOPp->in_instruction 
-						    >> 0x14U)));
-    vlTOPp->out_rd2 = ((IData)(vlTOPp->in_src2_fwd)
-		        ? vlTOPp->in_src2_fwd_data : 
-		       vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers
-		       [vlTOPp->out_rs2]);
-    vlTOPp->out_csr_mask = (((IData)(vlTOPp->VX_decode__DOT__is_csr) 
-			     & (vlTOPp->in_instruction 
-				>> 0xeU)) ? (IData)(vlTOPp->out_rs1)
-			     : vlTOPp->out_rd1);
-    // ALWAYS at VX_decode.v:247
-    vlTOPp->out_jal_offset = ((0x6fU == (0x7fU & vlTOPp->in_instruction))
-			       ? ((0xffe00000U & (VL_NEGATE_I((IData)(
-								      (1U 
-								       & (vlTOPp->in_instruction 
-									  >> 0x1fU)))) 
-						  << 0x15U)) 
-				  | ((0x100000U & (vlTOPp->in_instruction 
-						   >> 0xbU)) 
-				     | ((0xff000U & vlTOPp->in_instruction) 
-					| ((0x800U 
-					    & (vlTOPp->in_instruction 
-					       >> 9U)) 
-					   | (0x7feU 
-					      & (vlTOPp->in_instruction 
-						 >> 0x14U))))))
-			       : ((0x67U == (0x7fU 
-					     & vlTOPp->in_instruction))
-				   ? ((0xfffff000U 
-				       & (VL_NEGATE_I((IData)(
-							      (1U 
-							       & ((IData)(vlTOPp->VX_decode__DOT__jalr_immed) 
-								  >> 0xbU)))) 
-					  << 0xcU)) 
-				      | (IData)(vlTOPp->VX_decode__DOT__jalr_immed))
-				   : ((0x73U == (0x7fU 
-						 & vlTOPp->in_instruction))
-				       ? (((0U == (7U 
-						   & (vlTOPp->in_instruction 
-						      >> 0xcU))) 
-					   & (2U > 
-					      (0xfffU 
-					       & (vlTOPp->in_instruction 
-						  >> 0x14U))))
-					   ? 0xb0000000U
-					   : 0xdeadbeefU)
-				       : 0xdeadbeefU)));
-    // ALWAYS at VX_decode.v:295
-    vlTOPp->out_itype_immed = ((0x40U & vlTOPp->in_instruction)
-			        ? ((0x20U & vlTOPp->in_instruction)
-				    ? ((0x10U & vlTOPp->in_instruction)
-				        ? 0xdeadbeefU
-				        : ((8U & vlTOPp->in_instruction)
-					    ? 0xdeadbeefU
-					    : ((4U 
-						& vlTOPp->in_instruction)
-					        ? 0xdeadbeefU
-					        : (
-						   (2U 
-						    & vlTOPp->in_instruction)
-						    ? 
-						   ((1U 
-						     & vlTOPp->in_instruction)
-						     ? 
-						    ((0xfffff000U 
-						      & (VL_NEGATE_I((IData)(
-									     (1U 
-									      & (vlTOPp->in_instruction 
-										>> 0x1fU)))) 
-							 << 0xcU)) 
-						     | ((0x800U 
-							 & (vlTOPp->in_instruction 
-							    >> 0x14U)) 
-							| ((0x400U 
-							    & (vlTOPp->in_instruction 
-							       << 3U)) 
-							   | ((0x3f0U 
-							       & (vlTOPp->in_instruction 
-								  >> 0x15U)) 
-							      | (0xfU 
-								 & (vlTOPp->in_instruction 
-								    >> 8U))))))
-						     : 0xdeadbeefU)
-						    : 0xdeadbeefU))))
-				    : 0xdeadbeefU) : 
-			       ((0x20U & vlTOPp->in_instruction)
-				 ? ((0x10U & vlTOPp->in_instruction)
-				     ? 0xdeadbeefU : 
-				    ((8U & vlTOPp->in_instruction)
-				      ? 0xdeadbeefU
-				      : ((4U & vlTOPp->in_instruction)
-					  ? 0xdeadbeefU
-					  : ((2U & vlTOPp->in_instruction)
-					      ? ((1U 
-						  & vlTOPp->in_instruction)
-						  ? 
-						 ((0xfffff000U 
-						   & (VL_NEGATE_I((IData)(
-									  (1U 
-									   & (vlTOPp->in_instruction 
-									      >> 0x1fU)))) 
-						      << 0xcU)) 
-						  | ((0xfe0U 
-						      & (vlTOPp->in_instruction 
-							 >> 0x14U)) 
-						     | (IData)(vlTOPp->out_rd)))
-						  : 0xdeadbeefU)
-					      : 0xdeadbeefU))))
-				 : ((0x10U & vlTOPp->in_instruction)
-				     ? ((8U & vlTOPp->in_instruction)
-					 ? 0xdeadbeefU
-					 : ((4U & vlTOPp->in_instruction)
-					     ? 0xdeadbeefU
-					     : ((2U 
-						 & vlTOPp->in_instruction)
-						 ? 
-						((1U 
-						  & vlTOPp->in_instruction)
-						  ? 
-						 ((0xfffff000U 
-						   & (VL_NEGATE_I((IData)(
-									  (1U 
-									   & ((IData)(vlTOPp->VX_decode__DOT__alu_tempp) 
-									      >> 0xbU)))) 
-						      << 0xcU)) 
-						  | (IData)(vlTOPp->VX_decode__DOT__alu_tempp))
-						  : 0xdeadbeefU)
-						 : 0xdeadbeefU)))
-				     : ((8U & vlTOPp->in_instruction)
-					 ? 0xdeadbeefU
-					 : ((4U & vlTOPp->in_instruction)
-					     ? 0xdeadbeefU
-					     : ((2U 
-						 & vlTOPp->in_instruction)
-						 ? 
-						((1U 
-						  & vlTOPp->in_instruction)
-						  ? 
-						 ((0xfffff000U 
-						   & (VL_NEGATE_I((IData)(
-									  (1U 
-									   & (vlTOPp->in_instruction 
-									      >> 0x1fU)))) 
-						      << 0xcU)) 
-						  | (0xfffU 
-						     & (vlTOPp->in_instruction 
-							>> 0x14U)))
-						  : 0xdeadbeefU)
-						 : 0xdeadbeefU))))));
-}
-
-VL_INLINE_OPT void VVX_decode::_sequent__TOP__3(VVX_decode__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_decode::_sequent__TOP__3\n"); );
-    VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Variables
-    // Begin mtask footprint  all: 
-    VL_SIG8(__Vdlyvdim0__VX_decode__DOT__vx_register_file__DOT__registers__v0,4,0);
-    VL_SIG8(__Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0,0,0);
-    VL_SIG(__Vdlyvval__VX_decode__DOT__vx_register_file__DOT__registers__v0,31,0);
-    // Body
-    __Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0 = 0U;
-    // ALWAYS at VX_register_file.v:30
-    if (((0U != (IData)(vlTOPp->in_wb)) & (0U != (IData)(vlTOPp->in_rd)))) {
-	__Vdlyvval__VX_decode__DOT__vx_register_file__DOT__registers__v0 
-	    = vlTOPp->in_write_data;
-	__Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0 = 1U;
-	__Vdlyvdim0__VX_decode__DOT__vx_register_file__DOT__registers__v0 
-	    = vlTOPp->in_rd;
-    }
-    // ALWAYSPOST at VX_register_file.v:32
-    if (__Vdlyvset__VX_decode__DOT__vx_register_file__DOT__registers__v0) {
-	vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers[__Vdlyvdim0__VX_decode__DOT__vx_register_file__DOT__registers__v0] 
-	    = __Vdlyvval__VX_decode__DOT__vx_register_file__DOT__registers__v0;
-    }
-}
-
-VL_INLINE_OPT void VVX_decode::_combo__TOP__4(VVX_decode__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_decode::_combo__TOP__4\n"); );
-    VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    vlTOPp->out_rd2 = ((IData)(vlTOPp->in_src2_fwd)
-		        ? vlTOPp->in_src2_fwd_data : 
-		       vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers
-		       [vlTOPp->out_rs2]);
-    vlTOPp->out_rd1 = ((0x6fU == (0x7fU & vlTOPp->in_instruction))
-		        ? vlTOPp->in_curr_PC : ((IData)(vlTOPp->in_src1_fwd)
-						 ? vlTOPp->in_src1_fwd_data
-						 : 
-						vlTOPp->VX_decode__DOT__vx_register_file__DOT__registers
-						[vlTOPp->out_rs1]));
-    vlTOPp->out_csr_mask = (((IData)(vlTOPp->VX_decode__DOT__is_csr) 
-			     & (vlTOPp->in_instruction 
-				>> 0xeU)) ? (IData)(vlTOPp->out_rs1)
-			     : vlTOPp->out_rd1);
-}
-
-void VVX_decode::_eval(VVX_decode__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_decode::_eval\n"); );
-    VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    vlTOPp->_combo__TOP__1(vlSymsp);
-    if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
-	vlTOPp->_sequent__TOP__3(vlSymsp);
-    }
-    vlTOPp->_combo__TOP__4(vlSymsp);
-    // Final
-    vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
-}
-
-void VVX_decode::_eval_initial(VVX_decode__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_decode::_eval_initial\n"); );
-    VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
-}
-
-void VVX_decode::final() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_decode::final\n"); );
-    // Variables
-    VVX_decode__Syms* __restrict vlSymsp = this->__VlSymsp;
-    VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-}
-
-void VVX_decode::_eval_settle(VVX_decode__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_decode::_eval_settle\n"); );
-    VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    vlTOPp->_settle__TOP__2(vlSymsp);
-}
-
-VL_INLINE_OPT QData VVX_decode::_change_request(VVX_decode__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_decode::_change_request\n"); );
-    VVX_decode* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    // Change detection
-    QData __req = false;  // Logically a bool
-    return __req;
-}
-
-#ifdef VL_DEBUG
-void VVX_decode::_eval_debug_assertions() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_decode::_eval_debug_assertions\n"); );
-    // Body
-    if (VL_UNLIKELY((clk & 0xfeU))) {
-	Verilated::overWidthError("clk");}
-    if (VL_UNLIKELY((in_rd & 0xe0U))) {
-	Verilated::overWidthError("in_rd");}
-    if (VL_UNLIKELY((in_wb & 0xfcU))) {
-	Verilated::overWidthError("in_wb");}
-    if (VL_UNLIKELY((in_src1_fwd & 0xfeU))) {
-	Verilated::overWidthError("in_src1_fwd");}
-    if (VL_UNLIKELY((in_src2_fwd & 0xfeU))) {
-	Verilated::overWidthError("in_src2_fwd");}
-}
-#endif // VL_DEBUG
-
-void VVX_decode::_ctor_var_reset() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_decode::_ctor_var_reset\n"); );
-    // Body
-    clk = VL_RAND_RESET_I(1);
-    in_instruction = VL_RAND_RESET_I(32);
-    in_curr_PC = VL_RAND_RESET_I(32);
-    in_write_data = VL_RAND_RESET_I(32);
-    in_rd = VL_RAND_RESET_I(5);
-    in_wb = VL_RAND_RESET_I(2);
-    in_src1_fwd = VL_RAND_RESET_I(1);
-    in_src1_fwd_data = VL_RAND_RESET_I(32);
-    in_src2_fwd = VL_RAND_RESET_I(1);
-    in_src2_fwd_data = VL_RAND_RESET_I(32);
-    out_csr_address = VL_RAND_RESET_I(12);
-    out_is_csr = VL_RAND_RESET_I(1);
-    out_csr_mask = VL_RAND_RESET_I(32);
-    out_rd = VL_RAND_RESET_I(5);
-    out_rs1 = VL_RAND_RESET_I(5);
-    out_rd1 = VL_RAND_RESET_I(32);
-    out_rs2 = VL_RAND_RESET_I(5);
-    out_rd2 = VL_RAND_RESET_I(32);
-    out_wb = VL_RAND_RESET_I(2);
-    out_alu_op = VL_RAND_RESET_I(4);
-    out_rs2_src = VL_RAND_RESET_I(1);
-    out_itype_immed = VL_RAND_RESET_I(32);
-    out_mem_read = VL_RAND_RESET_I(3);
-    out_mem_write = VL_RAND_RESET_I(3);
-    out_branch_type = VL_RAND_RESET_I(3);
-    out_branch_stall = VL_RAND_RESET_I(1);
-    out_jal = VL_RAND_RESET_I(1);
-    out_jal_offset = VL_RAND_RESET_I(32);
-    out_upper_immed = VL_RAND_RESET_I(20);
-    out_PC_next = VL_RAND_RESET_I(32);
-    VX_decode__DOT__is_itype = VL_RAND_RESET_I(1);
-    VX_decode__DOT__is_csr = VL_RAND_RESET_I(1);
-    VX_decode__DOT__jalr_immed = VL_RAND_RESET_I(12);
-    VX_decode__DOT__alu_tempp = VL_RAND_RESET_I(12);
-    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    VX_decode__DOT__vx_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
-    }}
-}

rtl/obj_dir/VVX_decode.h

@@ -1,118 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Primary design header
-//
-// This header should be included by all source files instantiating the design.
-// The class here is then constructed to instantiate the design.
-// See the Verilator manual for examples.
-
-#ifndef _VVX_decode_H_
-#define _VVX_decode_H_
-
-#include "verilated.h"
-
-class VVX_decode__Syms;
-
-//----------
-
-VL_MODULE(VVX_decode) {
-  public:
-    
-    // PORTS
-    // The application code writes and reads these signals to
-    // propagate new values into/out from the Verilated model.
-    // Begin mtask footprint  all: 
-    VL_IN8(clk,0,0);
-    VL_IN8(in_rd,4,0);
-    VL_IN8(in_wb,1,0);
-    VL_IN8(in_src1_fwd,0,0);
-    VL_IN8(in_src2_fwd,0,0);
-    VL_OUT8(out_is_csr,0,0);
-    VL_OUT8(out_rd,4,0);
-    VL_OUT8(out_rs1,4,0);
-    VL_OUT8(out_rs2,4,0);
-    VL_OUT8(out_wb,1,0);
-    VL_OUT8(out_alu_op,3,0);
-    VL_OUT8(out_rs2_src,0,0);
-    VL_OUT8(out_mem_read,2,0);
-    VL_OUT8(out_mem_write,2,0);
-    VL_OUT8(out_branch_type,2,0);
-    VL_OUT8(out_branch_stall,0,0);
-    VL_OUT8(out_jal,0,0);
-    VL_OUT16(out_csr_address,11,0);
-    VL_IN(in_instruction,31,0);
-    VL_IN(in_curr_PC,31,0);
-    VL_IN(in_write_data,31,0);
-    VL_IN(in_src1_fwd_data,31,0);
-    VL_IN(in_src2_fwd_data,31,0);
-    VL_OUT(out_csr_mask,31,0);
-    VL_OUT(out_rd1,31,0);
-    VL_OUT(out_rd2,31,0);
-    VL_OUT(out_itype_immed,31,0);
-    VL_OUT(out_jal_offset,31,0);
-    VL_OUT(out_upper_immed,19,0);
-    VL_OUT(out_PC_next,31,0);
-    
-    // LOCAL SIGNALS
-    // Internals; generally not touched by application code
-    // Begin mtask footprint  all: 
-    VL_SIG8(VX_decode__DOT__is_itype,0,0);
-    VL_SIG8(VX_decode__DOT__is_csr,0,0);
-    VL_SIG16(VX_decode__DOT__jalr_immed,11,0);
-    VL_SIG16(VX_decode__DOT__alu_tempp,11,0);
-    VL_SIG(VX_decode__DOT__vx_register_file__DOT__registers[32],31,0);
-    
-    // LOCAL VARIABLES
-    // Internals; generally not touched by application code
-    // Begin mtask footprint  all: 
-    VL_SIG8(__Vclklast__TOP__clk,0,0);
-    
-    // INTERNAL VARIABLES
-    // Internals; generally not touched by application code
-    VVX_decode__Syms* __VlSymsp;  // Symbol table
-    
-    // PARAMETERS
-    // Parameters marked /*verilator public*/ for use by application code
-    
-    // CONSTRUCTORS
-  private:
-    VL_UNCOPYABLE(VVX_decode);  ///< Copying not allowed
-  public:
-    /// Construct the model; called by application code
-    /// The special name  may be used to make a wrapper with a
-    /// single model invisible with respect to DPI scope names.
-    VVX_decode(const char* name="TOP");
-    /// Destroy the model; called (often implicitly) by application code
-    ~VVX_decode();
-    
-    // API METHODS
-    /// Evaluate the model.  Application must call when inputs change.
-    void eval();
-    /// Simulation complete, run final blocks.  Application must call on completion.
-    void final();
-    
-    // INTERNAL METHODS
-  private:
-    static void _eval_initial_loop(VVX_decode__Syms* __restrict vlSymsp);
-  public:
-    void __Vconfigure(VVX_decode__Syms* symsp, bool first);
-  private:
-    static QData _change_request(VVX_decode__Syms* __restrict vlSymsp);
-  public:
-    static void _combo__TOP__1(VVX_decode__Syms* __restrict vlSymsp);
-    static void _combo__TOP__4(VVX_decode__Syms* __restrict vlSymsp);
-  private:
-    void _ctor_var_reset();
-  public:
-    static void _eval(VVX_decode__Syms* __restrict vlSymsp);
-  private:
-#ifdef VL_DEBUG
-    void _eval_debug_assertions();
-#endif // VL_DEBUG
-  public:
-    static void _eval_initial(VVX_decode__Syms* __restrict vlSymsp);
-    static void _eval_settle(VVX_decode__Syms* __restrict vlSymsp);
-    static void _sequent__TOP__3(VVX_decode__Syms* __restrict vlSymsp);
-    static void _settle__TOP__2(VVX_decode__Syms* __restrict vlSymsp);
-} VL_ATTR_ALIGNED(128);
-
-#endif // guard

rtl/obj_dir/VVX_decode.mk

@@ -1,53 +0,0 @@
-# Verilated -*- Makefile -*-
-# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
-#
-# Execute this makefile from the object directory:
-#    make -f VVX_decode.mk
-
-default: VVX_decode__ALL.a
-
-### Constants...
-# Perl executable (from $PERL)
-PERL = perl
-# Path to Verilator kit (from $VERILATOR_ROOT)
-VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
-# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
-SYSTEMC_INCLUDE ?= 
-# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
-SYSTEMC_LIBDIR ?= 
-
-### Switches...
-# SystemC output mode?  0/1 (from --sc)
-VM_SC = 0
-# Legacy or SystemC output mode?  0/1 (from --sc)
-VM_SP_OR_SC = $(VM_SC)
-# Deprecated
-VM_PCLI = 1
-# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
-VM_SC_TARGET_ARCH = linux
-
-### Vars...
-# Design prefix (from --prefix)
-VM_PREFIX = VVX_decode
-# Module prefix (from --prefix)
-VM_MODPREFIX = VVX_decode
-# User CFLAGS (from -CFLAGS on Verilator command line)
-VM_USER_CFLAGS = \
-
-# User LDLIBS (from -LDFLAGS on Verilator command line)
-VM_USER_LDLIBS = \
-
-# User .cpp files (from .cpp's on Verilator command line)
-VM_USER_CLASSES = \
-
-# User .cpp directories (from .cpp's on Verilator command line)
-VM_USER_DIR = \
-
-
-### Default rules...
-# Include list of all generated classes
-include VVX_decode_classes.mk
-# Include global rules
-include $(VERILATOR_ROOT)/include/verilated.mk
-
-# Verilated -*- Makefile -*-

rtl/obj_dir/VVX_decode__Syms.cpp

@@ -1,19 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Symbol table implementation internals
-
-#include "VVX_decode__Syms.h"
-#include "VVX_decode.h"
-
-// FUNCTIONS
-VVX_decode__Syms::VVX_decode__Syms(VVX_decode* topp, const char* namep)
-	// Setup locals
-	: __Vm_namep(namep)
-	, __Vm_didInit(false)
-	// Setup submodule names
-{
-    // Pointer to top level
-    TOPp = topp;
-    // Setup each module's pointers to their submodules
-    // Setup each module's pointer back to symbol table (for public functions)
-    TOPp->__Vconfigure(this, true);
-}

rtl/obj_dir/VVX_decode__Syms.h

@@ -1,34 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Symbol table internal header
-//
-// Internal details; most calling programs do not need this header
-
-#ifndef _VVX_decode__Syms_H_
-#define _VVX_decode__Syms_H_
-
-#include "verilated.h"
-
-// INCLUDE MODULE CLASSES
-#include "VVX_decode.h"
-
-// SYMS CLASS
-class VVX_decode__Syms : public VerilatedSyms {
-  public:
-    
-    // LOCAL STATE
-    const char* __Vm_namep;
-    bool __Vm_didInit;
-    
-    // SUBCELL STATE
-    VVX_decode*                    TOPp;
-    
-    // CREATORS
-    VVX_decode__Syms(VVX_decode* topp, const char* namep);
-    ~VVX_decode__Syms() {}
-    
-    // METHODS
-    inline const char* name() { return __Vm_namep; }
-    
-} VL_ATTR_ALIGNED(64);
-
-#endif // guard

rtl/obj_dir/VVX_decode__ver.d

@@ -1 +0,0 @@
-obj_dir/VVX_decode.cpp obj_dir/VVX_decode.h obj_dir/VVX_decode.mk obj_dir/VVX_decode__Syms.cpp obj_dir/VVX_decode__Syms.h obj_dir/VVX_decode__ver.d obj_dir/VVX_decode_classes.mk  : /usr/local/Cellar/verilator/4.010/bin/verilator_bin   /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_decode.v VX_register_file.v 

rtl/obj_dir/VVX_decode__verFiles.dat

@@ -1,13 +0,0 @@
-# DESCRIPTION: Verilator output: Timestamp data for --skip-identical.  Delete at will.
-C "-Wall -cc VX_decode.v VX_register_file.v"
-S   4608404 12889046060  1553037052           0  1548678579           0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
-S      9277 12889063385  1553149232           0  1553149232           0 "VX_decode.v"
-S       726 12889070228  1553138880           0  1553138880           0 "VX_register_file.v"
-T     30372 12889070221  1553149234           0  1553149234           0 "obj_dir/VVX_decode.cpp"
-T      3820 12889070220  1553149234           0  1553149234           0 "obj_dir/VVX_decode.h"
-T      1476 12889070223  1553149234           0  1553149234           0 "obj_dir/VVX_decode.mk"
-T       545 12889070219  1553149234           0  1553149234           0 "obj_dir/VVX_decode__Syms.cpp"
-T       732 12889070218  1553149234           0  1553149234           0 "obj_dir/VVX_decode__Syms.h"
-T       319 12889070301  1553149234           0  1553149234           0 "obj_dir/VVX_decode__ver.d"
-T         0        0  1553149234           0  1553149234           0 "obj_dir/VVX_decode__verFiles.dat"
-T      1168 12889070222  1553149234           0  1553149234           0 "obj_dir/VVX_decode_classes.mk"

rtl/obj_dir/VVX_decode_classes.mk

@@ -1,38 +0,0 @@
-# Verilated -*- Makefile -*-
-# DESCRIPTION: Verilator output: Make include file with class lists
-#
-# This file lists generated Verilated files, for including in higher level makefiles.
-# See VVX_decode.mk for the caller.
-
-### Switches...
-# Coverage output mode?  0/1 (from --coverage)
-VM_COVERAGE = 0
-# Threaded output mode?  0/1/N threads (from --threads)
-VM_THREADS = 0
-# Tracing output mode?  0/1 (from --trace)
-VM_TRACE = 0
-
-### Object file lists...
-# Generated module classes, fast-path, compile with highest optimization
-VM_CLASSES_FAST += \
-	VVX_decode \
-
-# Generated module classes, non-fast-path, compile with low/medium optimization
-VM_CLASSES_SLOW += \
-
-# Generated support classes, fast-path, compile with highest optimization
-VM_SUPPORT_FAST += \
-
-# Generated support classes, non-fast-path, compile with low/medium optimization
-VM_SUPPORT_SLOW += \
-	VVX_decode__Syms \
-
-# Global classes, need linked once per executable, fast-path, compile with highest optimization
-VM_GLOBAL_FAST += \
-	verilated \
-
-# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
-VM_GLOBAL_SLOW += \
-
-
-# Verilated -*- Makefile -*-

rtl/obj_dir/VVX_register_file.cpp

@@ -1,200 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Design implementation internals
-// See VVX_register_file.h for the primary calling header
-
-#include "VVX_register_file.h"
-#include "VVX_register_file__Syms.h"
-
-
-//--------------------
-// STATIC VARIABLES
-
-
-//--------------------
-
-VL_CTOR_IMP(VVX_register_file) {
-    VVX_register_file__Syms* __restrict vlSymsp = __VlSymsp = new VVX_register_file__Syms(this, name());
-    VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Reset internal values
-    
-    // Reset structure values
-    _ctor_var_reset();
-}
-
-void VVX_register_file::__Vconfigure(VVX_register_file__Syms* vlSymsp, bool first) {
-    if (0 && first) {}  // Prevent unused
-    this->__VlSymsp = vlSymsp;
-}
-
-VVX_register_file::~VVX_register_file() {
-    delete __VlSymsp; __VlSymsp=NULL;
-}
-
-//--------------------
-
-
-void VVX_register_file::eval() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_register_file::eval\n"); );
-    VVX_register_file__Syms* __restrict vlSymsp = this->__VlSymsp;  // Setup global symbol table
-    VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-#ifdef VL_DEBUG
-    // Debug assertions
-    _eval_debug_assertions();
-#endif // VL_DEBUG
-    // Initialize
-    if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
-    // Evaluate till stable
-    int __VclockLoop = 0;
-    QData __Vchange = 1;
-    do {
-	VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
-	_eval(vlSymsp);
-	if (VL_UNLIKELY(++__VclockLoop > 100)) {
-	    // About to fail, so enable debug to see what's not settling.
-	    // Note you must run make with OPT=-DVL_DEBUG for debug prints.
-	    int __Vsaved_debug = Verilated::debug();
-	    Verilated::debug(1);
-	    __Vchange = _change_request(vlSymsp);
-	    Verilated::debug(__Vsaved_debug);
-	    VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
-	} else {
-	    __Vchange = _change_request(vlSymsp);
-	}
-    } while (VL_UNLIKELY(__Vchange));
-}
-
-void VVX_register_file::_eval_initial_loop(VVX_register_file__Syms* __restrict vlSymsp) {
-    vlSymsp->__Vm_didInit = true;
-    _eval_initial(vlSymsp);
-    // Evaluate till stable
-    int __VclockLoop = 0;
-    QData __Vchange = 1;
-    do {
-	_eval_settle(vlSymsp);
-	_eval(vlSymsp);
-	if (VL_UNLIKELY(++__VclockLoop > 100)) {
-	    // About to fail, so enable debug to see what's not settling.
-	    // Note you must run make with OPT=-DVL_DEBUG for debug prints.
-	    int __Vsaved_debug = Verilated::debug();
-	    Verilated::debug(1);
-	    __Vchange = _change_request(vlSymsp);
-	    Verilated::debug(__Vsaved_debug);
-	    VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
-	} else {
-	    __Vchange = _change_request(vlSymsp);
-	}
-    } while (VL_UNLIKELY(__Vchange));
-}
-
-//--------------------
-// Internal Methods
-
-VL_INLINE_OPT void VVX_register_file::_sequent__TOP__1(VVX_register_file__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_register_file::_sequent__TOP__1\n"); );
-    VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Variables
-    // Begin mtask footprint  all: 
-    VL_SIG8(__Vdlyvdim0__VX_register_file__DOT__registers__v0,4,0);
-    VL_SIG8(__Vdlyvset__VX_register_file__DOT__registers__v0,0,0);
-    VL_SIG(__Vdlyvval__VX_register_file__DOT__registers__v0,31,0);
-    // Body
-    __Vdlyvset__VX_register_file__DOT__registers__v0 = 0U;
-    // ALWAYS at VX_register_file.v:30
-    if (((IData)(vlTOPp->in_write_register) & (0U != (IData)(vlTOPp->in_rd)))) {
-	__Vdlyvval__VX_register_file__DOT__registers__v0 
-	    = vlTOPp->in_data;
-	__Vdlyvset__VX_register_file__DOT__registers__v0 = 1U;
-	__Vdlyvdim0__VX_register_file__DOT__registers__v0 
-	    = vlTOPp->in_rd;
-    }
-    // ALWAYSPOST at VX_register_file.v:32
-    if (__Vdlyvset__VX_register_file__DOT__registers__v0) {
-	vlTOPp->VX_register_file__DOT__registers[__Vdlyvdim0__VX_register_file__DOT__registers__v0] 
-	    = __Vdlyvval__VX_register_file__DOT__registers__v0;
-    }
-}
-
-VL_INLINE_OPT void VVX_register_file::_settle__TOP__2(VVX_register_file__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_register_file::_settle__TOP__2\n"); );
-    VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    vlTOPp->out_src1_data = vlTOPp->VX_register_file__DOT__registers
-	[vlTOPp->in_src1];
-    vlTOPp->out_src2_data = vlTOPp->VX_register_file__DOT__registers
-	[vlTOPp->in_src2];
-}
-
-void VVX_register_file::_eval(VVX_register_file__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_register_file::_eval\n"); );
-    VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
-	vlTOPp->_sequent__TOP__1(vlSymsp);
-    }
-    vlTOPp->_settle__TOP__2(vlSymsp);
-    // Final
-    vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
-}
-
-void VVX_register_file::_eval_initial(VVX_register_file__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_register_file::_eval_initial\n"); );
-    VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
-}
-
-void VVX_register_file::final() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_register_file::final\n"); );
-    // Variables
-    VVX_register_file__Syms* __restrict vlSymsp = this->__VlSymsp;
-    VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-}
-
-void VVX_register_file::_eval_settle(VVX_register_file__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_register_file::_eval_settle\n"); );
-    VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    vlTOPp->_settle__TOP__2(vlSymsp);
-}
-
-VL_INLINE_OPT QData VVX_register_file::_change_request(VVX_register_file__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_register_file::_change_request\n"); );
-    VVX_register_file* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    // Change detection
-    QData __req = false;  // Logically a bool
-    return __req;
-}
-
-#ifdef VL_DEBUG
-void VVX_register_file::_eval_debug_assertions() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_register_file::_eval_debug_assertions\n"); );
-    // Body
-    if (VL_UNLIKELY((clk & 0xfeU))) {
-	Verilated::overWidthError("clk");}
-    if (VL_UNLIKELY((in_write_register & 0xfeU))) {
-	Verilated::overWidthError("in_write_register");}
-    if (VL_UNLIKELY((in_rd & 0xe0U))) {
-	Verilated::overWidthError("in_rd");}
-    if (VL_UNLIKELY((in_src1 & 0xe0U))) {
-	Verilated::overWidthError("in_src1");}
-    if (VL_UNLIKELY((in_src2 & 0xe0U))) {
-	Verilated::overWidthError("in_src2");}
-}
-#endif // VL_DEBUG
-
-void VVX_register_file::_ctor_var_reset() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVX_register_file::_ctor_var_reset\n"); );
-    // Body
-    clk = VL_RAND_RESET_I(1);
-    in_write_register = VL_RAND_RESET_I(1);
-    in_rd = VL_RAND_RESET_I(5);
-    in_data = VL_RAND_RESET_I(32);
-    in_src1 = VL_RAND_RESET_I(5);
-    in_src2 = VL_RAND_RESET_I(5);
-    out_src1_data = VL_RAND_RESET_I(32);
-    out_src2_data = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<32; ++__Vi0) {
-	    VX_register_file__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
-    }}
-}

rtl/obj_dir/VVX_register_file.h

@@ -1,88 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Primary design header
-//
-// This header should be included by all source files instantiating the design.
-// The class here is then constructed to instantiate the design.
-// See the Verilator manual for examples.
-
-#ifndef _VVX_register_file_H_
-#define _VVX_register_file_H_
-
-#include "verilated.h"
-
-class VVX_register_file__Syms;
-
-//----------
-
-VL_MODULE(VVX_register_file) {
-  public:
-    
-    // PORTS
-    // The application code writes and reads these signals to
-    // propagate new values into/out from the Verilated model.
-    // Begin mtask footprint  all: 
-    VL_IN8(clk,0,0);
-    VL_IN8(in_write_register,0,0);
-    VL_IN8(in_rd,4,0);
-    VL_IN8(in_src1,4,0);
-    VL_IN8(in_src2,4,0);
-    VL_IN(in_data,31,0);
-    VL_OUT(out_src1_data,31,0);
-    VL_OUT(out_src2_data,31,0);
-    
-    // LOCAL SIGNALS
-    // Internals; generally not touched by application code
-    // Begin mtask footprint  all: 
-    VL_SIG(VX_register_file__DOT__registers[32],31,0);
-    
-    // LOCAL VARIABLES
-    // Internals; generally not touched by application code
-    // Begin mtask footprint  all: 
-    VL_SIG8(__Vclklast__TOP__clk,0,0);
-    
-    // INTERNAL VARIABLES
-    // Internals; generally not touched by application code
-    VVX_register_file__Syms* __VlSymsp;  // Symbol table
-    
-    // PARAMETERS
-    // Parameters marked /*verilator public*/ for use by application code
-    
-    // CONSTRUCTORS
-  private:
-    VL_UNCOPYABLE(VVX_register_file);  ///< Copying not allowed
-  public:
-    /// Construct the model; called by application code
-    /// The special name  may be used to make a wrapper with a
-    /// single model invisible with respect to DPI scope names.
-    VVX_register_file(const char* name="TOP");
-    /// Destroy the model; called (often implicitly) by application code
-    ~VVX_register_file();
-    
-    // API METHODS
-    /// Evaluate the model.  Application must call when inputs change.
-    void eval();
-    /// Simulation complete, run final blocks.  Application must call on completion.
-    void final();
-    
-    // INTERNAL METHODS
-  private:
-    static void _eval_initial_loop(VVX_register_file__Syms* __restrict vlSymsp);
-  public:
-    void __Vconfigure(VVX_register_file__Syms* symsp, bool first);
-  private:
-    static QData _change_request(VVX_register_file__Syms* __restrict vlSymsp);
-    void _ctor_var_reset();
-  public:
-    static void _eval(VVX_register_file__Syms* __restrict vlSymsp);
-  private:
-#ifdef VL_DEBUG
-    void _eval_debug_assertions();
-#endif // VL_DEBUG
-  public:
-    static void _eval_initial(VVX_register_file__Syms* __restrict vlSymsp);
-    static void _eval_settle(VVX_register_file__Syms* __restrict vlSymsp);
-    static void _sequent__TOP__1(VVX_register_file__Syms* __restrict vlSymsp);
-    static void _settle__TOP__2(VVX_register_file__Syms* __restrict vlSymsp);
-} VL_ATTR_ALIGNED(128);
-
-#endif // guard

rtl/obj_dir/VVX_register_file.mk

@@ -1,53 +0,0 @@
-# Verilated -*- Makefile -*-
-# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
-#
-# Execute this makefile from the object directory:
-#    make -f VVX_register_file.mk
-
-default: VVX_register_file__ALL.a
-
-### Constants...
-# Perl executable (from $PERL)
-PERL = perl
-# Path to Verilator kit (from $VERILATOR_ROOT)
-VERILATOR_ROOT = /usr/local/Cellar/verilator/4.010/share/verilator
-# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
-SYSTEMC_INCLUDE ?= 
-# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
-SYSTEMC_LIBDIR ?= 
-
-### Switches...
-# SystemC output mode?  0/1 (from --sc)
-VM_SC = 0
-# Legacy or SystemC output mode?  0/1 (from --sc)
-VM_SP_OR_SC = $(VM_SC)
-# Deprecated
-VM_PCLI = 1
-# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
-VM_SC_TARGET_ARCH = linux
-
-### Vars...
-# Design prefix (from --prefix)
-VM_PREFIX = VVX_register_file
-# Module prefix (from --prefix)
-VM_MODPREFIX = VVX_register_file
-# User CFLAGS (from -CFLAGS on Verilator command line)
-VM_USER_CFLAGS = \
-
-# User LDLIBS (from -LDFLAGS on Verilator command line)
-VM_USER_LDLIBS = \
-
-# User .cpp files (from .cpp's on Verilator command line)
-VM_USER_CLASSES = \
-
-# User .cpp directories (from .cpp's on Verilator command line)
-VM_USER_DIR = \
-
-
-### Default rules...
-# Include list of all generated classes
-include VVX_register_file_classes.mk
-# Include global rules
-include $(VERILATOR_ROOT)/include/verilated.mk
-
-# Verilated -*- Makefile -*-

rtl/obj_dir/VVX_register_file__Syms.cpp

@@ -1,19 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Symbol table implementation internals
-
-#include "VVX_register_file__Syms.h"
-#include "VVX_register_file.h"
-
-// FUNCTIONS
-VVX_register_file__Syms::VVX_register_file__Syms(VVX_register_file* topp, const char* namep)
-	// Setup locals
-	: __Vm_namep(namep)
-	, __Vm_didInit(false)
-	// Setup submodule names
-{
-    // Pointer to top level
-    TOPp = topp;
-    // Setup each module's pointers to their submodules
-    // Setup each module's pointer back to symbol table (for public functions)
-    TOPp->__Vconfigure(this, true);
-}

rtl/obj_dir/VVX_register_file__Syms.h

@@ -1,34 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Symbol table internal header
-//
-// Internal details; most calling programs do not need this header
-
-#ifndef _VVX_register_file__Syms_H_
-#define _VVX_register_file__Syms_H_
-
-#include "verilated.h"
-
-// INCLUDE MODULE CLASSES
-#include "VVX_register_file.h"
-
-// SYMS CLASS
-class VVX_register_file__Syms : public VerilatedSyms {
-  public:
-    
-    // LOCAL STATE
-    const char* __Vm_namep;
-    bool __Vm_didInit;
-    
-    // SUBCELL STATE
-    VVX_register_file*             TOPp;
-    
-    // CREATORS
-    VVX_register_file__Syms(VVX_register_file* topp, const char* namep);
-    ~VVX_register_file__Syms() {}
-    
-    // METHODS
-    inline const char* name() { return __Vm_namep; }
-    
-} VL_ATTR_ALIGNED(64);
-
-#endif // guard

rtl/obj_dir/VVX_register_file__ver.d

@@ -1 +0,0 @@
-obj_dir/VVX_register_file.cpp obj_dir/VVX_register_file.h obj_dir/VVX_register_file.mk obj_dir/VVX_register_file__Syms.cpp obj_dir/VVX_register_file__Syms.h obj_dir/VVX_register_file__ver.d obj_dir/VVX_register_file_classes.mk  : /usr/local/Cellar/verilator/4.010/bin/verilator_bin   /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_register_file.v 

rtl/obj_dir/VVX_register_file__verFiles.dat

@@ -1,12 +0,0 @@
-# DESCRIPTION: Verilator output: Timestamp data for --skip-identical.  Delete at will.
-C "-Wall -cc VX_register_file.v"
-S   4608404 12889046060  1553037052           0  1548678579           0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
-S       726 12889070228  1553138880           0  1553138880           0 "VX_register_file.v"
-T      7234 12889070262  1553138884           0  1553138884           0 "obj_dir/VVX_register_file.cpp"
-T      2914 12889070261  1553138884           0  1553138884           0 "obj_dir/VVX_register_file.h"
-T      1511 12889070264  1553138884           0  1553138884           0 "obj_dir/VVX_register_file.mk"
-T       580 12889070260  1553138884           0  1553138884           0 "obj_dir/VVX_register_file__Syms.cpp"
-T       781 12889070259  1553138884           0  1553138884           0 "obj_dir/VVX_register_file__Syms.h"
-T       356 12889070265  1553138884           0  1553138884           0 "obj_dir/VVX_register_file__ver.d"
-T         0        0  1553138884           0  1553138884           0 "obj_dir/VVX_register_file__verFiles.dat"
-T      1189 12889070263  1553138884           0  1553138884           0 "obj_dir/VVX_register_file_classes.mk"

rtl/obj_dir/VVX_register_file_classes.mk

@@ -1,38 +0,0 @@
-# Verilated -*- Makefile -*-
-# DESCRIPTION: Verilator output: Make include file with class lists
-#
-# This file lists generated Verilated files, for including in higher level makefiles.
-# See VVX_register_file.mk for the caller.
-
-### Switches...
-# Coverage output mode?  0/1 (from --coverage)
-VM_COVERAGE = 0
-# Threaded output mode?  0/1/N threads (from --threads)
-VM_THREADS = 0
-# Tracing output mode?  0/1 (from --trace)
-VM_TRACE = 0
-
-### Object file lists...
-# Generated module classes, fast-path, compile with highest optimization
-VM_CLASSES_FAST += \
-	VVX_register_file \
-
-# Generated module classes, non-fast-path, compile with low/medium optimization
-VM_CLASSES_SLOW += \
-
-# Generated support classes, fast-path, compile with highest optimization
-VM_SUPPORT_FAST += \
-
-# Generated support classes, non-fast-path, compile with low/medium optimization
-VM_SUPPORT_SLOW += \
-	VVX_register_file__Syms \
-
-# Global classes, need linked once per executable, fast-path, compile with highest optimization
-VM_GLOBAL_FAST += \
-	verilated \
-
-# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
-VM_GLOBAL_SLOW += \
-
-
-# Verilated -*- Makefile -*-

rtl/obj_dir/Vvortex.h

@@ -5,16 +5,16 @@
 // The class here is then constructed to instantiate the design.
 // See the Verilator manual for examples.
 
-#ifndef _Vvortex_H_
+#ifndef _VVortex_H_
-#define _Vvortex_H_
+#define _VVortex_H_
 
-#include "verilated_heavy.h"
+#include "verilated.h"
 
-class Vvortex__Syms;
+class VVortex__Syms;
 
 //----------
 
-VL_MODULE(Vvortex) {
+VL_MODULE(VVortex) {
   public:
     
     // PORTS
@@ -23,24 +23,103 @@ VL_MODULE(Vvortex) {
     // Begin mtask footprint  all: 
     VL_IN8(clk,0,0);
     VL_IN8(reset,0,0);
-    VL_OUT8(fe_delay,0,0);
+    VL_OUT8(out_cache_driver_in_mem_read,2,0);
+    VL_OUT8(out_cache_driver_in_mem_write,2,0);
     VL_IN(fe_instruction,31,0);
+    VL_IN(in_cache_driver_out_data,31,0);
     VL_OUT(curr_PC,31,0);
-    VL_OUT(de_instruction,31,0);
+    VL_OUT(out_cache_driver_in_address,31,0);
+    VL_OUT(out_cache_driver_in_data,31,0);
     
     // LOCAL SIGNALS
     // Internals; generally not touched by application code
-    // Begin mtask footprint  all: 
+    // Anonymous structures to workaround compiler member-count bugs
-    VL_SIG8(vortex__DOT__vx_fetch__DOT__stall_reg,0,0);
+    struct {
-    VL_SIG8(vortex__DOT__vx_fetch__DOT__delay_reg,0,0);
+	// Begin mtask footprint  all: 
-    VL_SIG8(vortex__DOT__vx_fetch__DOT__state,4,0);
+	VL_SIG8(Vortex__DOT__decode_branch_type,2,0);
-    VL_SIG8(vortex__DOT__vx_fetch__DOT__prev_debug,0,0);
+	VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
-    VL_SIG(vortex__DOT__vx_fetch__DOT__old,31,0);
+	VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
-    VL_SIG(vortex__DOT__vx_fetch__DOT__real_PC,31,0);
+	VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
-    VL_SIG(vortex__DOT__vx_fetch__DOT__JAL_reg,31,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall_reg,0,0);
-    VL_SIG(vortex__DOT__vx_fetch__DOT__BR_reg,31,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__delay_reg,0,0);
-    VL_SIG(vortex__DOT__vx_fetch__DOT__PC_to_use,31,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__state,4,0);
-    VL_SIG(vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
+	VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid,0,0);
+	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
+	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,3,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rs2_src,0,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_read,2,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__mem_write,2,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__branch_type,2,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__is_csr,0,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__jal,0,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid,0,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__stalling,0,0);
+	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__rd,4,0);
+	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__wb,1,0);
+	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_read,2,0);
+	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__mem_write,2,0);
+	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__is_csr,0,0);
+	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__branch_type,2,0);
+	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__jal,0,0);
+	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid,0,0);
+	VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__rd,4,0);
+	VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__wb,1,0);
+	VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid,0,0);
+	VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd,0,0);
+	VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd,0,0);
+	VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd,0,0);
+	VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd,0,0);
+	VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd,0,0);
+	VL_SIG8(Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd,0,0);
+	VL_SIG16(Vortex__DOT__decode_csr_address,11,0);
+	VL_SIG16(Vortex__DOT__vx_decode__DOT__alu_tempp,11,0);
+	VL_SIG16(Vortex__DOT__vx_d_e_reg__DOT__csr_address,11,0);
+	VL_SIG16(Vortex__DOT__vx_e_m_reg__DOT__csr_address,11,0);
+	VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
+	VL_SIG(Vortex__DOT__decode_rd1,31,0);
+	VL_SIG(Vortex__DOT__decode_itype_immed,31,0);
+	VL_SIG(Vortex__DOT__execute_alu_result,31,0);
+	VL_SIG(Vortex__DOT__memory_branch_dest,31,0);
+	VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0);
+	VL_SIG(Vortex__DOT__vx_fetch__DOT__old,31,0);
+	VL_SIG(Vortex__DOT__vx_fetch__DOT__real_PC,31,0);
+	VL_SIG(Vortex__DOT__vx_fetch__DOT__JAL_reg,31,0);
+	VL_SIG(Vortex__DOT__vx_fetch__DOT__BR_reg,31,0);
+	VL_SIG(Vortex__DOT__vx_fetch__DOT__PC_to_use,31,0);
+	VL_SIG(Vortex__DOT__vx_fetch__DOT__temp_PC,31,0);
+	VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
+	VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd1,31,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd2,31,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
+    };
+    struct {
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
+	VL_SIG(Vortex__DOT__vx_execute__DOT__ALU_in2,31,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result,31,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__rd2,31,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__PC_next,31,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__csr_result,31,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__curr_PC,31,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__branch_offset,31,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__jal_dest,31,0);
+	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result,31,0);
+	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result,31,0);
+	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__PC_next,31,0);
+	VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
+	VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[32],31,0);
+	VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
+    };
     
     // LOCAL VARIABLES
     // Internals; generally not touched by application code
@@ -50,21 +129,21 @@ VL_MODULE(Vvortex) {
     
     // INTERNAL VARIABLES
     // Internals; generally not touched by application code
-    Vvortex__Syms* __VlSymsp;  // Symbol table
+    VVortex__Syms* __VlSymsp;  // Symbol table
     
     // PARAMETERS
     // Parameters marked /*verilator public*/ for use by application code
     
     // CONSTRUCTORS
   private:
-    VL_UNCOPYABLE(Vvortex);  ///< Copying not allowed
+    VL_UNCOPYABLE(VVortex);  ///< Copying not allowed
   public:
     /// Construct the model; called by application code
     /// The special name  may be used to make a wrapper with a
     /// single model invisible with respect to DPI scope names.
-    Vvortex(const char* name="TOP");
+    VVortex(const char* name="TOP");
     /// Destroy the model; called (often implicitly) by application code
-    ~Vvortex();
+    ~VVortex();
     
     // API METHODS
     /// Evaluate the model.  Application must call when inputs change.
@@ -74,27 +153,29 @@ VL_MODULE(Vvortex) {
     
     // INTERNAL METHODS
   private:
-    static void _eval_initial_loop(Vvortex__Syms* __restrict vlSymsp);
+    static void _eval_initial_loop(VVortex__Syms* __restrict vlSymsp);
   public:
-    void __Vconfigure(Vvortex__Syms* symsp, bool first);
+    void __Vconfigure(VVortex__Syms* symsp, bool first);
+  private:
+    static QData _change_request(VVortex__Syms* __restrict vlSymsp);
+  public:
+    static void _combo__TOP__6(VVortex__Syms* __restrict vlSymsp);
   private:
-    static QData _change_request(Vvortex__Syms* __restrict vlSymsp);
     void _ctor_var_reset();
   public:
-    static void _eval(Vvortex__Syms* __restrict vlSymsp);
+    static void _eval(VVortex__Syms* __restrict vlSymsp);
   private:
 #ifdef VL_DEBUG
     void _eval_debug_assertions();
 #endif // VL_DEBUG
   public:
-    static void _eval_initial(Vvortex__Syms* __restrict vlSymsp);
+    static void _eval_initial(VVortex__Syms* __restrict vlSymsp);
-    static void _eval_settle(Vvortex__Syms* __restrict vlSymsp);
+    static void _eval_settle(VVortex__Syms* __restrict vlSymsp);
-    static void _initial__TOP__4(Vvortex__Syms* __restrict vlSymsp);
+    static void _initial__TOP__3(VVortex__Syms* __restrict vlSymsp);
-    static void _sequent__TOP__2(Vvortex__Syms* __restrict vlSymsp);
+    static void _sequent__TOP__1(VVortex__Syms* __restrict vlSymsp);
-    static void _sequent__TOP__3(Vvortex__Syms* __restrict vlSymsp);
+    static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp);
-    static void _sequent__TOP__5(Vvortex__Syms* __restrict vlSymsp);
+    static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp);
-    static void _settle__TOP__1(Vvortex__Syms* __restrict vlSymsp);
+    static void _settle__TOP__4(VVortex__Syms* __restrict vlSymsp);
-    static void _settle__TOP__6(Vvortex__Syms* __restrict vlSymsp);
 } VL_ATTR_ALIGNED(128);
 
 #endif // guard

rtl/obj_dir/Vvortex.mk

@@ -2,9 +2,9 @@
 # DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
 #
 # Execute this makefile from the object directory:
-#    make -f Vvortex.mk
+#    make -f VVortex.mk
 
-default: Vvortex
+default: VVortex
 
 ### Constants...
 # Perl executable (from $PERL)
@@ -28,9 +28,9 @@ VM_SC_TARGET_ARCH = linux
 
 ### Vars...
 # Design prefix (from --prefix)
-VM_PREFIX = Vvortex
+VM_PREFIX = VVortex
 # Module prefix (from --prefix)
-VM_MODPREFIX = Vvortex
+VM_MODPREFIX = VVortex
 # User CFLAGS (from -CFLAGS on Verilator command line)
 VM_USER_CFLAGS = \
 
@@ -48,7 +48,7 @@ VM_USER_DIR = \
 
 ### Default rules...
 # Include list of all generated classes
-include Vvortex_classes.mk
+include VVortex_classes.mk
 # Include global rules
 include $(VERILATOR_ROOT)/include/verilated.mk
 
@@ -59,7 +59,7 @@ test_bench.o: test_bench.cpp
 	$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
 
 ### Link rules... (from --exe)
-Vvortex: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
+VVortex: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
 	$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS)
 
 

rtl/obj_dir/Vvortex__ALLcls.cpp

@@ -1,3 +1,3 @@
 // DESCRIPTION: Generated by verilator_includer via makefile
 #define VL_INCLUDE_OPT include
-#include "Vvortex.cpp"
+#include "VVortex.cpp"

rtl/obj_dir/Vvortex__ALLcls.d

@@ -1,5 +1,4 @@
-Vvortex__ALLcls.o: Vvortex__ALLcls.cpp Vvortex.cpp Vvortex.h \
+VVortex__ALLcls.o: VVortex__ALLcls.cpp VVortex.cpp VVortex.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
   /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
   /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
-  Vvortex__Syms.h
+  VVortex__Syms.h

rtl/obj_dir/Vvortex__ALLsup.cpp

@@ -1,3 +1,3 @@
 // DESCRIPTION: Generated by verilator_includer via makefile
 #define VL_INCLUDE_OPT include
-#include "Vvortex__Syms.cpp"
+#include "VVortex__Syms.cpp"

rtl/obj_dir/Vvortex__ALLsup.d

@@ -1,5 +1,4 @@
-Vvortex__ALLsup.o: Vvortex__ALLsup.cpp Vvortex__Syms.cpp Vvortex__Syms.h \
+VVortex__ALLsup.o: VVortex__ALLsup.cpp VVortex__Syms.cpp VVortex__Syms.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
   /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
   /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h \
-  Vvortex.h
+  VVortex.h

rtl/obj_dir/Vvortex__Syms.cpp

@@ -1,11 +1,11 @@
 // Verilated -*- C++ -*-
 // DESCRIPTION: Verilator output: Symbol table implementation internals
 
-#include "Vvortex__Syms.h"
+#include "VVortex__Syms.h"
-#include "Vvortex.h"
+#include "VVortex.h"
 
 // FUNCTIONS
-Vvortex__Syms::Vvortex__Syms(Vvortex* topp, const char* namep)
+VVortex__Syms::VVortex__Syms(VVortex* topp, const char* namep)
 	// Setup locals
 	: __Vm_namep(namep)
 	, __Vm_didInit(false)

rtl/obj_dir/Vvortex__Syms.h

@@ -3,16 +3,16 @@
 //
 // Internal details; most calling programs do not need this header
 
-#ifndef _Vvortex__Syms_H_
+#ifndef _VVortex__Syms_H_
-#define _Vvortex__Syms_H_
+#define _VVortex__Syms_H_
 
-#include "verilated_heavy.h"
+#include "verilated.h"
 
 // INCLUDE MODULE CLASSES
-#include "Vvortex.h"
+#include "VVortex.h"
 
 // SYMS CLASS
-class Vvortex__Syms : public VerilatedSyms {
+class VVortex__Syms : public VerilatedSyms {
   public:
     
     // LOCAL STATE
@@ -20,11 +20,11 @@ class Vvortex__Syms : public VerilatedSyms {
     bool __Vm_didInit;
     
     // SUBCELL STATE
-    Vvortex*                       TOPp;
+    VVortex*                       TOPp;
     
     // CREATORS
-    Vvortex__Syms(Vvortex* topp, const char* namep);
+    VVortex__Syms(VVortex* topp, const char* namep);
-    ~Vvortex__Syms() {}
+    ~VVortex__Syms() {}
     
     // METHODS
     inline const char* name() { return __Vm_namep; }

rtl/obj_dir/Vvortex__ver.d

@@ -1 +1 @@
-obj_dir/Vvortex.cpp obj_dir/Vvortex.h obj_dir/Vvortex.mk obj_dir/Vvortex__Syms.cpp obj_dir/Vvortex__Syms.h obj_dir/Vvortex__ver.d obj_dir/Vvortex_classes.mk  : /usr/local/Cellar/verilator/4.010/bin/verilator_bin   /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_f_d_reg.v VX_fetch.v vortex.v 
+obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk  : /usr/local/Cellar/verilator/4.010/bin/verilator_bin   /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_writeback.v Vortex.v 

rtl/obj_dir/Vvortex__verFiles.dat

@@ -1,14 +1,25 @@
 # DESCRIPTION: Verilator output: Timestamp data for --skip-identical.  Delete at will.
-C "-Wall -cc vortex.v VX_f_d_reg.v VX_fetch.v --exe test_bench.cpp"
+C "-Wall -cc Vortex.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp"
 S   4608404 12889046060  1553037052           0  1548678579           0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
-S       960 12889050060  1553112201           0  1553112201           0 "VX_f_d_reg.v"
+S      1495 12889087229  1553211178           0  1553211178           0 "VX_csr_handler.v"
+S      4626 12889079539  1553190875           0  1553190875           0 "VX_d_e_reg.v"
+S      8412 12889063385  1553211412           0  1553211412           0 "VX_decode.v"
+S      1351 12889079483  1553200040           0  1553200040           0 "VX_define.v"
+S      3644 12889083963  1553196174           0  1553196174           0 "VX_e_m_reg.v"
+S      4603 12889081819  1553208546           0  1553208546           0 "VX_execute.v"
+S       969 12889050060  1553223828           0  1553223828           0 "VX_f_d_reg.v"
 S      3337 12889047675  1553112414           0  1553112414           0 "VX_fetch.v"
-T     11853 12889064939  1553112478           0  1553112478           0 "obj_dir/Vvortex.cpp"
+S      4771 12889086478  1553200651           0  1553200651           0 "VX_forwarding.v"
-T      3513 12889064938  1553112478           0  1553112478           0 "obj_dir/Vvortex.h"
+S      1578 12889085814  1553211072           0  1553211072           0 "VX_m_w_reg.v"
-T      1800 12889064941  1553112478           0  1553112478           0 "obj_dir/Vvortex.mk"
+S      2315 12889084513  1553197906           0  1553197906           0 "VX_memory.v"
-T       530 12889064937  1553112478           0  1553112478           0 "obj_dir/Vvortex__Syms.cpp"
+S       726 12889070228  1553188094           0  1553188094           0 "VX_register_file.v"
-T       717 12889064936  1553112478           0  1553112478           0 "obj_dir/Vvortex__Syms.h"
+S       597 12889086287  1553199222           0  1553199222           0 "VX_writeback.v"
-T       300 12889064942  1553112478           0  1553112478           0 "obj_dir/Vvortex__ver.d"
+S     12863 12889050092  1553211358           0  1553211358           0 "Vortex.v"
-T         0        0  1553112478           0  1553112478           0 "obj_dir/Vvortex__verFiles.dat"
+T     77457 12889096617  1553223839           0  1553223839           0 "obj_dir/VVortex.cpp"
-T      1159 12889064940  1553112478           0  1553112478           0 "obj_dir/Vvortex_classes.mk"
+T      7575 12889096616  1553223839           0  1553223839           0 "obj_dir/VVortex.h"
-S      1826 12889050092  1553109861           0  1553109861           0 "vortex.v"
+T      1800 12889096619  1553223839           0  1553223839           0 "obj_dir/VVortex.mk"
+T       530 12889096615  1553223839           0  1553223839           0 "obj_dir/VVortex__Syms.cpp"
+T       711 12889096614  1553223839           0  1553223839           0 "obj_dir/VVortex__Syms.h"
+T       455 12889096620  1553223839           0  1553223839           0 "obj_dir/VVortex__ver.d"
+T         0        0  1553223839           0  1553223839           0 "obj_dir/VVortex__verFiles.dat"
+T      1159 12889096618  1553223839           0  1553223839           0 "obj_dir/VVortex_classes.mk"

rtl/obj_dir/Vvortex_classes.mk

@@ -2,7 +2,7 @@
 # DESCRIPTION: Verilator output: Make include file with class lists
 #
 # This file lists generated Verilated files, for including in higher level makefiles.
-# See Vvortex.mk for the caller.
+# See VVortex.mk for the caller.
 
 ### Switches...
 # Coverage output mode?  0/1 (from --coverage)
@@ -15,7 +15,7 @@ VM_TRACE = 0
 ### Object file lists...
 # Generated module classes, fast-path, compile with highest optimization
 VM_CLASSES_FAST += \
-	Vvortex \
+	VVortex \
 
 # Generated module classes, non-fast-path, compile with low/medium optimization
 VM_CLASSES_SLOW += \
@@ -25,7 +25,7 @@ VM_SUPPORT_FAST += \
 
 # Generated support classes, non-fast-path, compile with low/medium optimization
 VM_SUPPORT_SLOW += \
-	Vvortex__Syms \
+	VVortex__Syms \
 
 # Global classes, need linked once per executable, fast-path, compile with highest optimization
 VM_GLOBAL_FAST += \

rtl/obj_dir/test_bench.d

@@ -1,4 +1,4 @@
-test_bench.o: ../test_bench.cpp Vvortex.h \
+test_bench.o: ../test_bench.cpp ../test_bench.h ../VX_define.h ../ram.h \
-  /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated_heavy.h \
+  VVortex.h \
   /usr/local/Cellar/verilator/4.010/share/verilator/include/verilated.h \
   /usr/local/Cellar/verilator/4.010/share/verilator/include/verilatedos.h

rtl/ram.h

@@ -0,0 +1,235 @@
+
+#ifndef __RAM__
+
+#define __RAM__
+
+#include "string.h"
+
+class RAM{
+public:
+    uint8_t* mem[1 << 12];
+
+    RAM(){
+        for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL;
+    }
+    ~RAM(){
+        for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i];
+    }
+
+    void clear(){
+        for(uint32_t i = 0;i < (1 << 12);i++)
+        {
+            if(mem[i])
+            { 
+                delete mem[i];
+                mem[i] = NULL;
+            }
+        }
+    }
+
+    uint8_t* get(uint32_t address){
+
+        if(mem[address >> 20] == NULL) {
+            uint8_t* ptr = new uint8_t[1024*1024];
+            for(uint32_t i = 0;i < 1024*1024;i+=4) {
+                ptr[i + 0] = 0xFF;
+                ptr[i + 1] = 0xFF;
+                ptr[i + 2] = 0xFF;
+                ptr[i + 3] = 0xFF;
+            }
+            mem[address >> 20] = ptr;
+        }
+        return &mem[address >> 20][address & 0xFFFFF];
+    }
+
+    void read(uint32_t address,uint32_t length, uint8_t *data){
+        for(unsigned i = 0;i < length;i++){
+            data[i] = (*this)[address + i];
+        }
+    }
+
+    void write(uint32_t address,uint32_t length, uint8_t *data){
+        for(unsigned i = 0;i < length;i++){
+            (*this)[address + i] = data[i];
+        }
+    }
+
+    void getBlock(uint32_t address, uint8_t *data)
+    {
+        uint32_t block_number = address & 0xffffff00; // To zero out block offset
+        uint32_t bytes_num    = 256;
+
+        this->read(block_number, bytes_num, data);
+    }
+
+    void getWord(uint32_t address, uint32_t * data)
+    {
+        data[0] = 0;
+
+        uint8_t first  = *get(address + 0);
+        uint8_t second = *get(address + 1);
+        uint8_t third  = *get(address + 2);
+        uint8_t fourth = *get(address + 3);
+
+        // uint8_t hi = (uint8_t) *get(address + 0);
+        // std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << hi << "\n";
+        // hi = (uint8_t) *get(address + 1);
+        // std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << hi << "\n";
+        // hi = (uint8_t) *get(address + 2);
+        // std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << hi << "\n";
+        // hi = (uint8_t) *get(address + 3);
+        // std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << hi << "\n";
+
+        data[0] = (data[0] << 0) | fourth;
+        data[0] = (data[0] << 8) | third;
+        data[0] = (data[0] << 8) | second;
+        data[0] = (data[0] << 8) | first;
+
+    }
+
+    void writeWord(uint32_t address, uint32_t * data)
+    {
+        uint32_t data_to_write = *data;
+
+        uint32_t byte_mask = 0xFF;
+
+        for (int i = 0; i < 4; i++)
+        {
+            // std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
+            // std::cout << "RAM: DATA TO MASK  " << byte_mask << "\n";
+            // std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
+            (*this)[address + i] = data_to_write & byte_mask;
+            data_to_write        = data_to_write >> 8;
+        }
+    }
+
+    void writeHalf(uint32_t address, uint32_t * data)
+    {
+        uint32_t data_to_write = *data;
+
+        uint32_t byte_mask = 0xFF;
+
+        for (int i = 0; i < 2; i++)
+        {
+            // std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
+            // std::cout << "RAM: DATA TO MASK  " << byte_mask << "\n";
+            // std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
+            (*this)[address + i] = data_to_write & byte_mask;
+            data_to_write        = data_to_write >> 8;
+        }
+    }
+
+    void writeByte(uint32_t address, uint32_t * data)
+    {
+        uint32_t data_to_write = *data;
+
+        uint32_t byte_mask = 0xFF;
+
+        (*this)[address] = data_to_write & byte_mask;
+        data_to_write    = data_to_write >> 8;
+
+    }
+
+    uint8_t& operator [](uint32_t address) {
+        return *get(address);
+    }
+
+};
+
+
+// MEMORY UTILS
+
+uint32_t hti(char c) {
+    if (c >= 'A' && c <= 'F')
+        return c - 'A' + 10;
+    if (c >= 'a' && c <= 'f')
+        return c - 'a' + 10;
+    return c - '0';
+}
+
+uint32_t hToI(char *c, uint32_t size) {
+    uint32_t value = 0;
+    for (uint32_t i = 0; i < size; i++) {
+        value += hti(c[i]) << ((size - i - 1) * 4);
+    }
+    return value;
+}
+
+
+
+void loadHexImpl(std::string path,RAM* mem) {
+    mem->clear();
+    FILE *fp = fopen(&path[0], "r");
+    if(fp == 0){
+        std::cout << path << " not found" << std::endl;
+    }
+    //Preload 0x0 <-> 0x80000000 jumps
+    ((uint32_t*)mem->get(0))[1] = 0xf1401073;
+
+    // ((uint32_t*)mem->get(0))[1] = 0xf1401073;
+    ((uint32_t*)mem->get(0))[2] = 0x30101073;
+
+    ((uint32_t*)mem->get(0))[3] = 0x800000b7;
+    ((uint32_t*)mem->get(0))[4] = 0x000080e7;
+    
+    ((uint32_t*)mem->get(0x80000000))[0] = 0x00000097;
+
+    ((uint32_t*)mem->get(0xb0000000))[0] = 0x01C02023;
+    // F00FFF10
+    ((uint32_t*)mem->get(0xf00fff10))[0] = 0x12345678;
+
+
+    
+
+    fseek(fp, 0, SEEK_END);
+    uint32_t size = ftell(fp);
+    fseek(fp, 0, SEEK_SET);
+    char* content = new char[size];
+    fread(content, 1, size, fp);
+
+    int offset = 0;
+    char* line = content;
+    // std::cout << "WHTA\n";
+    while (1) {
+        if (line[0] == ':') {
+            uint32_t byteCount = hToI(line + 1, 2);
+            uint32_t nextAddr = hToI(line + 3, 4) + offset;
+            uint32_t key = hToI(line + 7, 2);
+            switch (key) {
+            case 0:
+                for (uint32_t i = 0; i < byteCount; i++) {
+
+                    unsigned add = nextAddr + i;
+
+                    *(mem->get(add)) = hToI(line + 9 + i * 2, 2);
+                    // std::cout << "Address: " << std::hex <<(add) << "\tValue: " << std::hex << hToI(line + 9 + i * 2, 2) << std::endl;
+                }
+                break;
+            case 2:
+//              cout << offset << endl;
+                offset = hToI(line + 9, 4) << 4;
+                break;
+            case 4:
+//              cout << offset << endl;
+                offset = hToI(line + 9, 4) << 16;
+                break;
+            default:
+//              cout << "??? " << key << endl;
+                break;
+            }
+        }
+
+        while (*line != '\n' && size != 0) {
+            line++;
+            size--;
+        }
+        if (size <= 1)
+            break;
+        line++;
+        size--;
+    }
+
+    if (content) delete[] content;
+}
+
+#endif

rtl/results.txt

@@ -0,0 +1,351 @@
+
+****************	../../src/riscv_tests/rv32ui-p-add.hex	****************
+# Dynamic Instructions: 597
+# of total cycles:      608
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.01843
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-addi.hex	****************
+# Dynamic Instructions: 312
+# of total cycles:      323
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.03526
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-and.hex	****************
+# Dynamic Instructions: 595
+# of total cycles:      606
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.01849
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-andi.hex	****************
+# Dynamic Instructions: 246
+# of total cycles:      257
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.04472
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-auipc.hex	****************
+# Dynamic Instructions: 65
+# of total cycles:      76
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.16923
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-beq.hex	****************
+# Dynamic Instructions: 431
+# of total cycles:      442
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.02552
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-bge.hex	****************
+# Dynamic Instructions: 467
+# of total cycles:      478
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.02355
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-bgeu.hex	****************
+# Dynamic Instructions: 492
+# of total cycles:      503
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.02236
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-blt.hex	****************
+# Dynamic Instructions: 431
+# of total cycles:      442
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.02552
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-bltu.hex	****************
+# Dynamic Instructions: 456
+# of total cycles:      467
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.02412
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-bne.hex	****************
+# Dynamic Instructions: 431
+# of total cycles:      442
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.02552
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-jal.hex	****************
+# Dynamic Instructions: 61
+# of total cycles:      72
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.18033
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-jalr.hex	****************
+# Dynamic Instructions: 138
+# of total cycles:      149
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.07971
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-lb.hex	****************
+# Dynamic Instructions: 135
+# of total cycles:      145
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.07407
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 25
+
+****************	../../src/riscv_tests/rv32ui-p-lbu.hex	****************
+# Dynamic Instructions: 135
+# of total cycles:      145
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.07407
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 25
+
+****************	../../src/riscv_tests/rv32ui-p-lh.hex	****************
+# Dynamic Instructions: 140
+# of total cycles:      150
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.07143
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 25
+
+****************	../../src/riscv_tests/rv32ui-p-lhu.hex	****************
+# Dynamic Instructions: 143
+# of total cycles:      153
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.06993
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 25
+
+****************	../../src/riscv_tests/rv32ui-p-lui.hex	****************
+# Dynamic Instructions: 55
+# of total cycles:      65
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.18182
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 7
+
+****************	../../src/riscv_tests/rv32ui-p-lui.hex.hex	****************
+# Dynamic Instructions: 55
+# of total cycles:      65
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.18182
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 7
+
+****************	../../src/riscv_tests/rv32ui-p-lw.hex	****************
+# Dynamic Instructions: 146
+# of total cycles:      156
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.06849
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 25
+
+****************	../../src/riscv_tests/rv32ui-p-or.hex	****************
+# Dynamic Instructions: 598
+# of total cycles:      609
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.01839
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-ori.hex	****************
+# Dynamic Instructions: 253
+# of total cycles:      264
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.04348
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-sb.hex	****************
+# Dynamic Instructions: 161
+# of total cycles:      171
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.06211
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 25
+
+****************	../../src/riscv_tests/rv32ui-p-sh.hex	****************
+# Dynamic Instructions: 502
+# of total cycles:      512
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.01992
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 43
+
+****************	../../src/riscv_tests/rv32ui-p-simple.hex	****************
+# Dynamic Instructions: 37
+# of total cycles:      48
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.2973
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-sll.hex	****************
+# Dynamic Instructions: 180
+# of total cycles:      190
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.05556
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 35
+
+****************	../../src/riscv_tests/rv32ui-p-slli.hex	****************
+# Dynamic Instructions: 311
+# of total cycles:      322
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.03537
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-slt.hex	****************
+# Dynamic Instructions: 591
+# of total cycles:      602
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.01861
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-slti.hex	****************
+# Dynamic Instructions: 307
+# of total cycles:      318
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.03583
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-sltiu.hex	****************
+# Dynamic Instructions: 307
+# of total cycles:      318
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.03583
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-sltu.hex	****************
+# Dynamic Instructions: 591
+# of total cycles:      602
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.01861
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-sra.hex	****************
+# Dynamic Instructions: 58
+# of total cycles:      68
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.17241
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 7
+
+****************	../../src/riscv_tests/rv32ui-p-srai.hex	****************
+# Dynamic Instructions: 56
+# of total cycles:      66
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.17857
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 7
+
+****************	../../src/riscv_tests/rv32ui-p-srl.hex	****************
+# Dynamic Instructions: 185
+# of total cycles:      195
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.05405
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 35
+
+****************	../../src/riscv_tests/rv32ui-p-srli.hex	****************
+# Dynamic Instructions: 320
+# of total cycles:      331
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.03438
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-sub.hex	****************
+# Dynamic Instructions: 587
+# of total cycles:      598
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.01874
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-sw.hex	****************
+# Dynamic Instructions: 152
+# of total cycles:      162
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.06579
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                Failed on test: 21
+
+****************	../../src/riscv_tests/rv32ui-p-xor.hex	****************
+# Dynamic Instructions: 597
+# of total cycles:      608
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.01843
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING
+
+****************	../../src/riscv_tests/rv32ui-p-xori.hex	****************
+# Dynamic Instructions: 255
+# of total cycles:      266
+# of forwarding stalls: 0
+# of branch stalls:     0
+# CPI:                  1.04314
+# time to simulate:     6.95312e-310 milliseconds
+# GRADE:                PASSING

rtl/test_bench.cpp

@@ -1,38 +1,77 @@
-#include "Vvortex.h"
-#include "verilated.h"
 
-#include <stdio.h>
 
-unsigned inst_array[10] = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19};
+#include "test_bench.h"
+
+#define NUM_TESTS 39
 
 int main(int argc, char **argv)
 {
+
 	Verilated::commandArgs(argc, argv);
 
-	Vvortex * vortex = new Vvortex;
 
-	vortex->clk = 0;
+	Vortex v;
-	vortex->reset = 1;
-	vortex->eval();
 
-	vortex->reset = 0;
+    bool passed = true;
+	std::string tests[NUM_TESTS] = {
+		"../../src/riscv_tests/rv32ui-p-add.hex",
+		"../../src/riscv_tests/rv32ui-p-addi.hex",
+		"../../src/riscv_tests/rv32ui-p-and.hex",
+		"../../src/riscv_tests/rv32ui-p-andi.hex",
+		"../../src/riscv_tests/rv32ui-p-auipc.hex",
+		"../../src/riscv_tests/rv32ui-p-beq.hex",
+		"../../src/riscv_tests/rv32ui-p-bge.hex",
+		"../../src/riscv_tests/rv32ui-p-bgeu.hex",
+		"../../src/riscv_tests/rv32ui-p-blt.hex",
+		"../../src/riscv_tests/rv32ui-p-bltu.hex",
+		"../../src/riscv_tests/rv32ui-p-bne.hex",
+		"../../src/riscv_tests/rv32ui-p-jal.hex",
+		"../../src/riscv_tests/rv32ui-p-jalr.hex",
+		"../../src/riscv_tests/rv32ui-p-lb.hex",
+		"../../src/riscv_tests/rv32ui-p-lbu.hex",
+		"../../src/riscv_tests/rv32ui-p-lh.hex",
+		"../../src/riscv_tests/rv32ui-p-lhu.hex",
+		"../../src/riscv_tests/rv32ui-p-lui.hex",
+		"../../src/riscv_tests/rv32ui-p-lui.hex.hex",
+		"../../src/riscv_tests/rv32ui-p-lw.hex",
+		"../../src/riscv_tests/rv32ui-p-or.hex",
+		"../../src/riscv_tests/rv32ui-p-ori.hex",
+		"../../src/riscv_tests/rv32ui-p-sb.hex",
+		"../../src/riscv_tests/rv32ui-p-sh.hex",
+		"../../src/riscv_tests/rv32ui-p-simple.hex",
+		"../../src/riscv_tests/rv32ui-p-sll.hex",
+		"../../src/riscv_tests/rv32ui-p-slli.hex",
+		"../../src/riscv_tests/rv32ui-p-slt.hex",
+		"../../src/riscv_tests/rv32ui-p-slti.hex",
+		"../../src/riscv_tests/rv32ui-p-sltiu.hex",
+		"../../src/riscv_tests/rv32ui-p-sltu.hex",
+		"../../src/riscv_tests/rv32ui-p-sra.hex",
+		"../../src/riscv_tests/rv32ui-p-srai.hex",
+		"../../src/riscv_tests/rv32ui-p-srl.hex",
+		"../../src/riscv_tests/rv32ui-p-srli.hex",
+		"../../src/riscv_tests/rv32ui-p-sub.hex",
+		"../../src/riscv_tests/rv32ui-p-sw.hex",
+		"../../src/riscv_tests/rv32ui-p-xor.hex",
+		"../../src/riscv_tests/rv32ui-p-xori.hex",
+	};
 
-	for (int i = 0; i < 10; i++)
+		for (int ii = 0; ii < NUM_TESTS; ii++)
-	{
+		// for (int ii = 0; ii < NUM_TESTS - 1; ii++)
+		{
+			bool curr = v.simulate(tests[ii]);
 
-		vortex->fe_instruction = inst_array[(vortex->curr_PC) / 4];
+			if ( curr) std::cout << GREEN << "Test Passed: " << tests[ii] << std::endl;
+			if (!curr) std::cout << RED   << "Test Failed: " << tests[ii] << std::endl;
+			passed = passed && curr;
 
-		vortex->clk = 1;
+			std::cout << DEFAULT;
-		vortex->eval();
+		}
 
-		vortex->clk = 0;
+		if( passed) std::cout << DEFAULT << "PASSED ALL TESTS\n";
-		vortex->eval();
+		if(!passed) std::cout << DEFAULT << "Failed one or more tests\n";
 
 		
-	}
+	// v.simulate("../../src/riscv_tests/rv32ui-p-add.hex");
-
-
-	delete vortex;
 
 	return 0;
 

rtl/test_bench.h

@@ -0,0 +1,314 @@
+
+
+// C++ libraries
+#include <utility> 
+#include <iostream>
+#include <map> 
+#include <iterator>
+#include <iomanip>
+#include <fstream>
+#include <unistd.h>
+#include <vector>
+#include <math.h>
+#include <algorithm>
+
+#include "VX_define.h"
+#include "ram.h"
+#include "VVortex.h"
+#include "verilated.h"
+
+
+
+class Vortex
+{
+    public:
+        Vortex();
+        ~Vortex();
+        bool simulate(std::string);
+    private:
+    	void ProcessFile(void);
+        void print_stats(bool = true);
+        bool ibus_driver();
+        bool dbus_driver();
+
+        RAM ram;
+
+        VVortex * vortex;
+
+        unsigned start_pc;
+        long int curr_cycle;
+        bool stop;
+        bool unit_test;
+        std::string instruction_file_name;
+        std::ofstream results;
+        int stats_static_inst;
+        int stats_dynamic_inst;
+        int stats_total_cycles;
+        int stats_fwd_stalls;
+        int stats_branch_stalls;
+        int debug_state;
+        int ibus_state;
+        int dbus_state;
+        int debug_return;
+        int debug_wait_num;
+        int debug_inst_num;
+        int debug_end_wait;
+        int debug_debugAddr;
+        double stats_sim_time;
+};
+
+
+
+Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
+                                                    stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
+                                                    debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
+                                                    debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
+{
+	this->vortex = new VVortex;
+    this->results.open("../results.txt");
+}
+
+Vortex::~Vortex()
+{
+	this->results.close();
+	delete this->vortex;
+}
+
+
+void Vortex::ProcessFile(void)
+{
+    loadHexImpl(this->instruction_file_name, &this->ram);
+}
+
+
+bool Vortex::ibus_driver()
+{
+    
+    ////////////////////// IBUS //////////////////////
+    unsigned new_PC;
+    bool stop = false;
+    uint32_t curr_inst = 0;
+
+    curr_inst = 0xdeadbeef;
+
+    new_PC                             = vortex->curr_PC;
+    ram.getWord(new_PC, &curr_inst);
+    vortex->fe_instruction      = curr_inst;
+
+    ////////////////////// IBUS //////////////////////
+
+
+    ////////////////////// STATS //////////////////////
+    ++stats_total_cycles;
+
+
+    if (((((unsigned int)curr_inst) != 0) && (((unsigned int)curr_inst) != 0xffffffff)) || (this->ibus_state == 1) || (this->dbus_state == 1))
+    {
+        ++stats_dynamic_inst;
+        stop = false;
+    } else
+    {
+        stop = true;
+    }
+
+    return stop;
+
+}
+
+
+
+bool Vortex::dbus_driver()
+{
+    uint32_t data_read;
+    uint32_t data_write;
+    uint32_t addr;
+    // std::cout << "DBUS DRIVER\n" << std::endl;
+    ////////////////////// DBUS //////////////////////
+
+
+    if (vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE)
+    {
+        data_write = (uint32_t) vortex->out_cache_driver_in_data;
+        addr       = (uint32_t) vortex->out_cache_driver_in_address;
+
+        if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
+        {
+        	data_write = ( data_write) & 0xFF;
+            ram.writeByte( addr, &data_write);
+
+        } else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE)
+        {
+            data_write = ( data_write) & 0xFFFF;
+            ram.writeHalf( addr, &data_write);
+        } else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE)
+        {
+            data_write = data_write;
+            ram.writeWord( addr, &data_write);
+        }
+
+    }
+
+    if (vortex->out_cache_driver_in_mem_read != NO_MEM_READ)
+    {
+
+        addr = (uint32_t) vortex->out_cache_driver_in_address;
+        ram.getWord(addr, &data_read);
+
+    	if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ)
+    	{
+
+            vortex->in_cache_driver_out_data = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF);
+
+    	} else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ)
+    	{
+
+            vortex->in_cache_driver_out_data = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF);
+
+    	} else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ)
+    	{
+
+            vortex->in_cache_driver_out_data = data_read;
+
+    	} else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
+    	{
+
+            vortex->in_cache_driver_out_data = (data_read & 0xFF);
+
+    	} else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ)
+    	{
+
+            vortex->in_cache_driver_out_data = (data_read & 0xFFFF);
+
+    	}
+    	else
+    	{
+            vortex->in_cache_driver_out_data = 0xbabebabe;
+    	}
+    }
+    else
+    {
+        vortex->in_cache_driver_out_data = 0xbabebabe;
+    }
+
+    return false;
+}
+
+
+
+bool Vortex::simulate(std::string file_to_simulate)
+{
+
+    this->instruction_file_name = file_to_simulate;
+    this->results << "\n****************\t" << file_to_simulate << "\t****************\n";
+
+    this->ProcessFile();
+
+    // auto start_time = std::chrono::high_resolution_clock::now();
+
+
+    static bool stop      = false;
+    static int counter    = 0;
+    counter = 0;
+    stop = false;
+
+    // auto start_time = clock();
+
+
+	vortex->clk = 0;
+	vortex->reset = 1;
+	vortex->eval();
+
+	vortex->reset = 0;
+
+	unsigned curr_inst;
+	unsigned new_PC;
+	while (this->stop && (!(stop && (counter > 5))))
+	{
+
+        bool istop =  ibus_driver();
+        bool dstop = !dbus_driver();
+        stop       =  istop && dstop;
+
+		vortex->clk = 1;
+		vortex->eval();
+
+		vortex->clk = 0;
+		vortex->eval();
+
+        if (stop)
+        {
+            counter++;
+        } else
+        {
+            counter = 0;
+        }
+
+	}
+
+    uint32_t status;
+    ram.getWord(0, &status);
+
+    this->print_stats();
+
+
+
+    return (status == 1);
+}
+
+
+void Vortex::print_stats(bool cycle_test)
+{
+
+    if (cycle_test)
+    {
+        this->results << std::left;
+        // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
+        this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
+        this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
+        this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
+        this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
+        this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
+        this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
+    }
+    else
+    {
+        this->results << std::left;
+        this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
+        this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
+    }
+
+
+    uint32_t status;
+    ram.getWord(0, &status);
+
+    if (this->unit_test)
+    {
+        if (status == 1)
+        {
+            this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
+        } else
+        {
+            this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
+        }
+    }
+    else
+    {
+        this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
+    }
+
+    this->stats_static_inst   =  0;
+    this->stats_dynamic_inst  = -1;
+    this->stats_total_cycles  =  0;
+    this->stats_fwd_stalls    =  0;
+    this->stats_branch_stalls =  0;
+
+}
+
+
+
+
+
+
+
+
+

rtl/vortex.v

@@ -1,89 +1,512 @@
 
-// `include "vx_fetch.v"
-// `include "vx_f_d_reg.v"
 
-module vortex(
+
+module Vortex(
 	input  wire       clk,
 	input  wire       reset,
 	input  wire[31:0] fe_instruction,
+	input  wire[31:0] in_cache_driver_out_data,
 	output wire[31:0] curr_PC,
-	output wire[31:0] de_instruction,
+	output wire[31:0] out_cache_driver_in_address,
-	output wire       fe_delay
+	output wire[2:0]  out_cache_driver_in_mem_read,
+	output wire[2:0]  out_cache_driver_in_mem_write,
+	output wire[31:0] out_cache_driver_in_data 
 	);
 
-wire branch_dir;
-assign branch_dir = 0;
 
-wire freeze;
+assign curr_PC = fetch_curr_PC;
-assign freeze = 0;
 
-wire[31:0] branch_dest;
+// From fetch
-wire       branch_stall;
+wire[31:0] fetch_instruction;
-wire       fwd_stall;
+wire       fetch_delay;
-wire       branch_stall_exe;
+wire[31:0] fetch_curr_PC;
-wire       jal;
+wire       fetch_valid;
-wire[31:0] jal_dest;
-wire       interrupt;
-wire       debug;
 
-assign branch_dest       = 32'h0;
+// From f_d_register
-assign branch_stall      = 1'b0;
+wire[31:0] f_d_instruction;
-assign fwd_stall         = 1'b0;
+wire[31:0] f_d_curr_PC;
-assign branch_stall_exe  = 1'b0;
+wire       f_d_valid;
-assign jal               = 1'b0;
+
-assign jal_dest          = 32'h0;
+// From decode
-assign interrupt         = 1'b0;
+wire       decode_branch_stall;
-assign debug             = 1'b0;
+wire[11:0] decode_csr_address;
+wire       decode_is_csr;
+wire[31:0] decode_csr_mask; 
+wire[4:0]  decode_rd;
+wire[4:0]  decode_rs1;
+wire[31:0] decode_rd1;
+wire[4:0]  decode_rs2;
+wire[31:0] decode_rd2;
+wire[1:0]  decode_wb;
+wire[3:0]  decode_alu_op;
+wire       decode_rs2_src; 
+reg[31:0]  decode_itype_immed; 
+wire[2:0]  decode_mem_read; 
+wire[2:0]  decode_mem_write; 
+reg[2:0]   decode_branch_type;
+reg        decode_jal;
+reg[31:0]  decode_jal_offset;
+reg[19:0]  decode_upper_immed;
+wire[31:0] decode_PC_next;
+wire       decode_valid;
+
+// From d_e_register
+wire[11:0] d_e_csr_address;
+wire       d_e_is_csr; 
+wire[31:0] d_e_csr_mask; 
+wire[4:0]  d_e_rd;
+wire[4:0]  d_e_rs1;
+wire[31:0] d_e_rd1;
+wire[4:0]  d_e_rs2;
+wire[31:0] d_e_rd2;
+wire[3:0]  d_e_alu_op;
+wire[1:0]  d_e_wb;
+wire       d_e_rs2_src;
+wire[31:0] d_e_itype_immed;
+wire[2:0]  d_e_mem_read;
+wire[2:0]  d_e_mem_write;
+wire[2:0]  d_e_branch_type;
+wire[19:0] d_e_upper_immed;
+wire[31:0] d_e_curr_PC;
+wire       d_e_jal;
+wire[31:0] d_e_jal_offset;
+wire[31:0] d_e_PC_next;
+wire       d_e_valid;
 
 
-wire[31:0] f_instruction;
+// From execute
-wire       f_delay; /* verilator lint_off UNUSED */
+wire       execute_branch_stall;
-wire[31:0] f_curr_pc;
+wire[11:0] execute_csr_address;
-wire       f_valid;
+wire       execute_is_csr;
-
+reg[31:0]  execute_csr_result;
-assign curr_PC = f_curr_pc;
+reg[31:0]  execute_alu_result;
-assign fe_delay = f_delay;
+wire[4:0]  execute_rd;
-
+wire[1:0]  execute_wb;
-VX_fetch vx_fetch (
+wire[4:0]  execute_rs1;
-	.clk(clk),
+wire[31:0] execute_rd1;
-	.reset(reset),
+wire[4:0]  execute_rs2;
-	.in_branch_dir(branch_dir),
+wire[31:0] execute_rd2;
-	.in_freeze(freeze),
+wire[2:0]  execute_mem_read;
-	.in_branch_dest(branch_dest),
+wire[2:0]  execute_mem_write;
-	.in_branch_stall(branch_stall),
+wire       execute_jal;
-	.in_fwd_stall(fwd_stall),
+wire[31:0] execute_jal_dest;
-	.in_branch_stall_exe(branch_stall_exe),
+wire[31:0] execute_branch_offset;
-	.in_jal(jal),
+wire[31:0] execute_PC_next;
-	.in_jal_dest(jal_dest),
+wire       execute_valid;
-	.in_interrupt(interrupt),
-	.in_debug(debug),
-	.in_instruction(fe_instruction),
-
-	.out_instruction(f_instruction),
-	.out_delay(f_delay),
-	.out_curr_PC(f_curr_pc),
-	.out_valid(f_valid)
-);
 
 
-wire[31:0] d_curr_pc;
+// From e_m_register
-wire[31:0] d_instruction;
+wire       e_m_jal;
-wire       d_valid;
+wire[31:0] e_m_jal_dest;
+wire[11:0] e_m_csr_address;
+wire       e_m_is_csr;
+wire[31:0] e_m_csr_result;
+wire[31:0] e_m_alu_result;
+wire[4:0]  e_m_rd;
+wire[1:0]  e_m_wb;
+wire[4:0]  e_m_rs1;
+/* verilator lint_off UNUSED */
+wire[31:0] e_m_rd1;
+/* verilator lint_on UNUSED */
+wire[31:0] e_m_rd2;
+wire[4:0]  e_m_rs2;
+wire[2:0]  e_m_mem_read;
+wire[2:0]  e_m_mem_write;
+wire[31:0] e_m_curr_PC;
+wire[31:0] e_m_branch_offset;
+wire[2:0]  e_m_branch_type;
+wire[31:0] e_m_PC_next;
+wire       e_m_valid;
 
-VX_f_d_reg vx_f_d_reg (
+
-	  .clk(clk),
+// From memory
-	  .reset(reset),
+wire       memory_delay;
-	  .in_instruction(f_instruction),
+wire       memory_branch_dir;
-	  .in_valid(f_valid),
+wire[31:0] memory_branch_dest;
-	  .in_curr_PC(f_curr_pc),
+wire[31:0] memory_alu_result;
-	  .in_fwd_stall(fwd_stall),
+wire[31:0] memory_mem_result;
-	  .in_freeze(freeze),
+wire[4:0]  memory_rd;
-	  .out_instruction(d_instruction),
+wire[1:0]  memory_wb;
-	  .out_curr_PC(d_curr_pc),
+wire[4:0]  memory_rs1;
-	  .out_valid(d_valid)
+wire[4:0]  memory_rs2;
+wire[31:0] memory_PC_next;
+wire       memory_valid;
+
+// From m_w_register
+wire[31:0] m_w_alu_result;
+wire[31:0] m_w_mem_result;
+wire[4:0]  m_w_rd;
+wire[1:0]  m_w_wb;
+/* verilator lint_off UNUSED */
+wire[4:0]  m_w_rs1;
+wire[4:0]  m_w_rs2;
+/* verilator lint_on UNUSED */
+wire[31:0] m_w_PC_next;
+wire       m_w_valid;
+
+// From writeback
+wire[31:0] writeback_write_data;
+wire[4:0]  writeback_rd;
+wire[1:0]  writeback_wb;
+
+// From csr handler
+wire[31:0]  csr_decode_csr_data;
+
+
+// From forwarding
+wire       forwarding_fwd_stall;
+wire       forwarding_src1_fwd;
+wire       forwarding_src2_fwd;
+/* verilator lint_off UNUSED */
+wire       forwarding_csr_fwd;
+wire[31:0] forwarding_csr_fwd_data;
+/* verilator lint_on UNUSED */
+wire[31:0] forwarding_src1_fwd_data;
+wire[31:0] forwarding_src2_fwd_data;
+
+
+// Internal
+wire total_freeze;
+wire interrupt;
+wire debug;
+
+assign debug        = 1'b0;
+assign interrupt    = 1'b0;
+assign total_freeze = fetch_delay || memory_delay;
+
+ 
+
+VX_fetch vx_fetch(
+		.clk(clk),
+		.reset(reset),
+		.in_branch_dir(memory_branch_dir),
+		.in_freeze(total_freeze),
+		.in_branch_dest(memory_branch_dest),
+		.in_branch_stall(decode_branch_stall),
+		.in_fwd_stall(forwarding_fwd_stall),
+		.in_branch_stall_exe(execute_branch_stall),
+		.in_jal(e_m_jal),
+		.in_jal_dest(e_m_jal_dest),
+		.in_interrupt(interrupt),
+		.in_debug(debug),
+		.in_instruction(fe_instruction),
+
+		.out_instruction(fetch_instruction),
+		.out_delay(fetch_delay),
+		.out_curr_PC(fetch_curr_PC),
+		.out_valid(fetch_valid)
 	);
 
-assign de_instruction = d_instruction;
+
+VX_f_d_reg vx_f_d_reg(
+		.clk(clk),
+		.reset(reset),
+		.in_instruction(fetch_instruction),
+		.in_valid(fetch_valid),
+		.in_curr_PC(fetch_curr_PC),
+		.in_fwd_stall(forwarding_fwd_stall),
+		.in_freeze(total_freeze),
+		.out_instruction(f_d_instruction),
+		.out_curr_PC(f_d_curr_PC),
+		.out_valid(f_d_valid)
+	);
+
+
+VX_decode vx_decode(
+		.clk(clk),
+		.in_instruction(f_d_instruction),
+		.in_curr_PC(f_d_curr_PC),
+		.in_valid(f_d_valid),
+		.in_write_data(writeback_write_data),
+		.in_rd(writeback_rd),
+		.in_wb(writeback_wb),
+
+		.in_src1_fwd(forwarding_src1_fwd),
+		.in_src1_fwd_data(forwarding_src1_fwd_data),
+		.in_src2_fwd(forwarding_src2_fwd),
+		.in_src2_fwd_data(forwarding_src2_fwd_data),
+
+		.out_csr_address(decode_csr_address),
+		.out_is_csr(decode_is_csr),
+		.out_csr_mask(decode_csr_mask),
+
+		.out_rd(decode_rd),
+		.out_rs1(decode_rs1),
+		.out_rd1(decode_rd1),
+		.out_rs2(decode_rs2),
+		.out_rd2(decode_rd2),
+		.out_wb(decode_wb),
+		.out_alu_op(decode_alu_op),
+		.out_rs2_src(decode_rs2_src),
+		.out_itype_immed(decode_itype_immed),
+		.out_mem_read(decode_mem_read),
+		.out_mem_write(decode_mem_write),
+		.out_branch_type(decode_branch_type),
+		.out_branch_stall(decode_branch_stall),
+		.out_jal(decode_jal),
+		.out_jal_offset(decode_jal_offset),
+		.out_upper_immed(decode_upper_immed),
+		.out_PC_next(decode_PC_next),
+		.out_valid(decode_valid)
+	);
+
+
+VX_d_e_reg vx_d_e_reg(
+		.clk(clk),
+		.in_rd(decode_rd),
+		.in_rs1(decode_rs1),
+		.in_rd1(decode_rd1),
+		.in_rs2(decode_rs2),
+		.in_rd2(decode_rd2),
+		.in_alu_op(decode_alu_op),
+		.in_wb(decode_wb),
+		.in_rs2_src(decode_rs2_src), 
+		.in_itype_immed(decode_itype_immed), 
+		.in_mem_read(decode_mem_read), 
+		.in_mem_write(decode_mem_write),
+		.in_PC_next(decode_PC_next),
+		.in_branch_type(decode_branch_type),
+		.in_fwd_stall(forwarding_fwd_stall),
+		.in_branch_stall(execute_branch_stall),
+		.in_upper_immed(decode_upper_immed),
+		.in_csr_address(decode_csr_address),
+		.in_is_csr(decode_is_csr),
+		.in_csr_mask(decode_csr_mask),
+		.in_curr_PC(f_d_curr_PC),
+		.in_jal(decode_jal),
+		.in_jal_offset(decode_jal_offset),
+		.in_freeze(total_freeze),
+		.in_valid(decode_valid),
+
+		.out_csr_address(d_e_csr_address),
+		.out_is_csr(d_e_is_csr),
+		.out_csr_mask(d_e_csr_mask),
+		.out_rd(d_e_rd),
+		.out_rs1(d_e_rs1),
+		.out_rd1(d_e_rd1),
+		.out_rs2(d_e_rs2),
+		.out_rd2(d_e_rd2),
+		.out_alu_op(d_e_alu_op),
+		.out_wb(d_e_wb),
+		.out_rs2_src(d_e_rs2_src), 
+		.out_itype_immed(d_e_itype_immed), 
+		.out_mem_read(d_e_mem_read),
+		.out_mem_write(d_e_mem_write),
+		.out_branch_type(d_e_branch_type),
+		.out_upper_immed(d_e_upper_immed),
+		.out_curr_PC(d_e_curr_PC),
+		.out_jal(d_e_jal),
+		.out_jal_offset(d_e_jal_offset),
+		.out_PC_next(d_e_PC_next),
+		.out_valid(d_e_valid)
+	);
+
+VX_execute vx_execute(
+		.in_rd(d_e_rd),
+		.in_rs1(d_e_rs1),
+		.in_rd1(d_e_rd1),
+		.in_rs2(d_e_rs2),
+		.in_rd2(d_e_rd2),
+		.in_alu_op(d_e_alu_op),
+		.in_wb(d_e_wb),
+		.in_rs2_src(d_e_rs2_src),
+		.in_itype_immed(d_e_itype_immed),
+		.in_mem_read(d_e_mem_read),
+		.in_mem_write(d_e_mem_write),
+		.in_PC_next(d_e_PC_next),
+		.in_branch_type(d_e_branch_type),
+		.in_upper_immed(d_e_upper_immed),
+		.in_csr_address(d_e_csr_address),
+		.in_is_csr(d_e_is_csr),
+		.in_csr_data(csr_decode_csr_data),
+		.in_csr_mask(d_e_csr_mask),
+		.in_jal(d_e_jal),
+		.in_jal_offset(d_e_jal_offset),
+		.in_curr_PC(d_e_curr_PC),
+		.in_valid(d_e_valid),
+
+		.out_csr_address(execute_csr_address),
+		.out_is_csr(execute_is_csr),
+		.out_csr_result(execute_csr_result),
+		.out_alu_result(execute_alu_result),
+		.out_rd(execute_rd),
+		.out_wb(execute_wb),
+		.out_rs1(execute_rs1),
+		.out_rd1(execute_rd1),
+		.out_rs2(execute_rs2),
+		.out_rd2(execute_rd2),
+		.out_mem_read(execute_mem_read),
+		.out_mem_write(execute_mem_write),
+		.out_jal(execute_jal),
+		.out_jal_dest(execute_jal_dest),
+		.out_branch_offset(execute_branch_offset),
+		.out_branch_stall(execute_branch_stall),
+		.out_PC_next(execute_PC_next),
+		.out_valid(execute_valid)
+	);
+
+
+VX_e_m_reg vx_e_m_reg(
+		.clk(clk),
+		.in_alu_result(execute_alu_result),
+		.in_rd(execute_rd),
+		.in_wb(execute_wb),
+		.in_rs1(execute_rs1),
+		.in_rd1(execute_rd1),
+		.in_rs2(execute_rs2),
+		.in_rd2(execute_rd2),
+		.in_mem_read(execute_mem_read),
+		.in_mem_write(execute_mem_write),
+		.in_PC_next(execute_PC_next),
+		.in_csr_address(execute_csr_address),
+		.in_is_csr(execute_is_csr),
+		.in_csr_result(execute_csr_result),
+		.in_curr_PC(d_e_curr_PC),
+		.in_branch_offset(execute_branch_offset),
+		.in_branch_type(d_e_branch_type),
+		.in_jal(execute_jal),
+		.in_jal_dest(execute_jal_dest),
+		.in_freeze(total_freeze),
+		.in_valid(execute_valid),
+
+		.out_csr_address(e_m_csr_address),
+		.out_is_csr(e_m_is_csr),
+		.out_csr_result(e_m_csr_result),
+		.out_alu_result(e_m_alu_result),
+		.out_rd(e_m_rd),
+		.out_wb(e_m_wb),
+		.out_rs1(e_m_rs1),
+		.out_rd1(e_m_rd1),
+		.out_rd2(e_m_rd2),
+		.out_rs2(e_m_rs2),
+		.out_mem_read(e_m_mem_read),
+		.out_mem_write(e_m_mem_write),
+		.out_curr_PC(e_m_curr_PC),
+		.out_branch_offset(e_m_branch_offset),
+		.out_branch_type(e_m_branch_type),
+		.out_jal(e_m_jal),
+		.out_jal_dest(e_m_jal_dest),
+		.out_PC_next(e_m_PC_next),
+		.out_valid(e_m_valid)
+	);
+
+VX_memory vx_memory(
+		.in_alu_result(e_m_alu_result),
+		.in_mem_read(e_m_mem_read), 
+		.in_mem_write(e_m_mem_write),
+		.in_rd(e_m_rd),
+		.in_wb(e_m_wb),
+		.in_rs1(e_m_rs1),
+		.in_rs2(e_m_rs2),
+		.in_rd2(e_m_rd2),
+		.in_PC_next(e_m_PC_next),
+		.in_curr_PC(e_m_curr_PC),
+		.in_branch_offset(e_m_branch_offset),
+		.in_branch_type(e_m_branch_type), 
+		.in_valid(e_m_valid),
+		.in_cache_driver_out_data(in_cache_driver_out_data),
+
+		.out_alu_result(memory_alu_result),
+		.out_mem_result(memory_mem_result),
+		.out_rd(memory_rd),
+		.out_wb(memory_wb),
+		.out_rs1(memory_rs1),
+		.out_rs2(memory_rs2),
+		.out_branch_dir(memory_branch_dir),
+		.out_branch_dest(memory_branch_dest),
+		.out_delay(memory_delay),
+		.out_PC_next(memory_PC_next),
+		.out_valid(memory_valid),
+		.out_cache_driver_in_address(out_cache_driver_in_address),
+		.out_cache_driver_in_mem_read(out_cache_driver_in_mem_read),
+		.out_cache_driver_in_mem_write(out_cache_driver_in_mem_write),
+		.out_cache_driver_in_data(out_cache_driver_in_data)
+	);
+
+VX_m_w_reg vx_m_w_reg(
+		.clk(clk),
+		.in_alu_result(memory_alu_result),
+		.in_mem_result(memory_mem_result),
+		.in_rd(memory_rd),
+		.in_wb(memory_wb),
+		.in_rs1(memory_rs1),
+		.in_rs2(memory_rs2),
+		.in_PC_next(memory_PC_next),
+		.in_freeze(total_freeze),
+		.in_valid(memory_valid),
+
+		.out_alu_result(m_w_alu_result),
+		.out_mem_result(m_w_mem_result),
+		.out_rd(m_w_rd),
+		.out_wb(m_w_wb),
+		.out_rs1(m_w_rs1),
+		.out_rs2(m_w_rs2),
+		.out_PC_next(m_w_PC_next),
+		.out_valid(m_w_valid)
+	);
+
+
+VX_writeback vx_writeback(
+		.in_alu_result(m_w_alu_result),
+		.in_mem_result(m_w_mem_result),
+		.in_rd(m_w_rd),
+		.in_wb(m_w_wb),
+		.in_PC_next(m_w_PC_next),
+
+		.out_write_data(writeback_write_data),
+		.out_rd(writeback_rd),
+		.out_wb(writeback_wb)
+	);
+
+
+VX_forwarding vx_forwarding(
+		.in_decode_src1(decode_rs1),
+		.in_decode_src2(decode_rs2),
+		.in_decode_csr_address(decode_csr_address), 
+
+		.in_execute_dest(execute_rd),
+		.in_execute_wb(execute_wb),
+		.in_execute_alu_result(execute_alu_result),
+		.in_execute_PC_next(execute_PC_next),
+		.in_execute_is_csr(execute_is_csr),
+		.in_execute_csr_address(execute_csr_address),
+
+		.in_memory_dest(memory_rd),
+		.in_memory_wb(memory_wb),
+		.in_memory_alu_result(memory_alu_result),
+		.in_memory_mem_data(memory_mem_result),
+		.in_memory_PC_next(memory_PC_next),
+		.in_memory_is_csr(e_m_is_csr),
+		.in_memory_csr_address(e_m_csr_address),
+		.in_memory_csr_result(e_m_csr_result),
+
+		.in_writeback_dest(m_w_rd),
+		.in_writeback_wb(m_w_wb),
+		.in_writeback_alu_result(m_w_alu_result),
+		.in_writeback_mem_data(m_w_mem_result),
+		.in_writeback_PC_next(m_w_PC_next),
+
+		.out_src1_fwd(forwarding_src1_fwd),
+		.out_src2_fwd(forwarding_src2_fwd),
+		.out_csr_fwd(forwarding_csr_fwd),
+		.out_src1_fwd_data(forwarding_src1_fwd_data),
+		.out_src2_fwd_data(forwarding_src2_fwd_data),
+		.out_csr_fwd_data(forwarding_csr_fwd_data),
+		.out_fwd_stall(forwarding_fwd_stall)
+	);
+
+VX_csr_handler vx_csr_handler(
+		.clk(clk),
+		.in_decode_csr_address(decode_csr_address),
+		.in_mem_csr_address(e_m_csr_address),
+		.in_mem_is_csr(e_m_is_csr),
+		.in_mem_csr_result(e_m_csr_result),
+		.in_wb_valid(m_w_valid),
+
+		.out_decode_csr_data(csr_decode_csr_data)
+	);
+
+
 
 
 endmodule // Vortex