45 lines
969 B
Verilog
45 lines
969 B
Verilog
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module VX_f_d_reg (
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input wire clk,
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input wire reset,
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input wire[31:0] in_instruction,
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input wire in_valid,
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input wire[31:0] in_curr_PC,
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input wire in_fwd_stall,
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input wire in_freeze,
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output wire[31:0] out_instruction,
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output wire[31:0] out_curr_PC,
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output wire out_valid
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);
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// always @(posedge clk) begin
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// $display("Fetch Inst: %d\tDecode Inst: %d", in_instruction, out_instruction);
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// end
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reg[31:0] instruction;
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reg[31:0] curr_PC;
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reg valid;
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always @(posedge clk or posedge reset) begin
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if(reset || (in_fwd_stall == 1'b1) || (in_freeze == 1'b1)) begin
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instruction <= 32'h0;
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curr_PC <= 32'h0;
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valid <= 1'b0;
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end else begin
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instruction <= in_instruction;
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valid <= in_valid;
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curr_PC <= in_curr_PC;
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end
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end
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assign out_instruction = instruction;
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assign out_curr_PC = curr_PC;
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assign out_valid = valid;
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endmodule |