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Using verilog For-loops + Passing all tests

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felsabbagh3
2019-03-30 22:14:44 -04:00
parent a3a3b21de7
commit 52a839f84d
12 changed files with 2379 additions and 587 deletions
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8
rtl/VX_fetch.v
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@@ -45,14 +45,14 @@ module VX_fetch (
reg[`NT_M1:0] valid;
// integer ini_cur_th = 0;
integer ini_cur_th = 0;
genvar out_cur_th;
initial begin
// for (ini_cur_th = 0; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
// valid[ini_cur_th] = 1; // Thread 1 active
for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
valid[ini_cur_th] = 0; // Thread 1 active
valid[0] = 1;
valid[1] = 0;
// valid[1] = 0;
stall_reg = 0;
delay_reg = 0;
old = 0;