diff --git a/rtl/VX_define.h b/rtl/VX_define.h
index 0ef8d8b6..2fd9f837 100644
--- a/rtl/VX_define.h
+++ b/rtl/VX_define.h
@@ -1,8 +1,7 @@
 
 
-#define NT 2
-#define NT_M1 1
-#define NT_T2_M1 3
+#define NT 5
+#define NT_M1 4
 
 #define R_INST 51
 #define L_INST 3
diff --git a/rtl/VX_define.v b/rtl/VX_define.v
index 5bc5b8ce..627c576d 100644
--- a/rtl/VX_define.v
+++ b/rtl/VX_define.v
@@ -1,7 +1,6 @@
 
-`define NT 2
-`define NT_M1 1
-`define NT_T2_M1 3
+`define NT 5
+`define NT_M1 4
 
 
 `define R_INST 7'd51
diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v
index e208adbf..835ea6fe 100644
--- a/rtl/VX_fetch.v
+++ b/rtl/VX_fetch.v
@@ -45,14 +45,14 @@ module VX_fetch (
 		reg[`NT_M1:0] valid;
 
 
-		// integer ini_cur_th = 0;
+		integer ini_cur_th = 0;
 		genvar out_cur_th;
 
 		initial begin
-			// for (ini_cur_th = 0; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
-			// 	valid[ini_cur_th]   = 1; // Thread 1 active
+			for (ini_cur_th = 1; ini_cur_th < `NT; ini_cur_th=ini_cur_th+1)
+				valid[ini_cur_th]   = 0; // Thread 1 active
 			valid[0]   = 1;
-			valid[1]   = 0;
+			// valid[1]   = 0;
 			stall_reg  = 0;
 			delay_reg  = 0;
 			old        = 0;
diff --git a/rtl/obj_dir/VVortex b/rtl/obj_dir/VVortex
index 66696e66..517a7088 100755
Binary files a/rtl/obj_dir/VVortex and b/rtl/obj_dir/VVortex differ
diff --git a/rtl/obj_dir/VVortex.cpp b/rtl/obj_dir/VVortex.cpp
index 67de734d..e1518546 100644
--- a/rtl/obj_dir/VVortex.cpp
+++ b/rtl/obj_dir/VVortex.cpp
@@ -97,12 +97,15 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
     // Variables
     // Begin mtask footprint  all: 
     VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0,0,0);
-    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0);
-    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2,0,0);
-    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v5,0,0);
+    VL_SIG8(__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v5,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v6,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v7,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v8,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v9,0,0);
     // Body
     __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 0U;
-    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 0U;
+    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v5 = 0U;
     // ALWAYS at VX_fetch.v:147
     vlTOPp->Vortex__DOT__vx_fetch__DOT__old = ((IData)(vlTOPp->reset)
 					        ? 0U
@@ -129,11 +132,20 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
 	__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0 = 1U;
     } else {
 	if ((1U & (~ (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)))) {
-	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 
+	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v5 
+		= vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid
+		[4U];
+	    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v5 = 1U;
+	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v6 
+		= vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid
+		[3U];
+	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v7 
+		= vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid
+		[2U];
+	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v8 
 		= vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid
 		[1U];
-	    __Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2 = 1U;
-	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3 
+	    __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v9 
 		= vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid
 		[0U];
 	}
@@ -161,13 +173,31 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
     if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v0) {
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] = 0U;
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] = 0U;
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[2U] = 0U;
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[3U] = 0U;
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[4U] = 0U;
     }
-    if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v2) {
+    if (__Vdlyvset__Vortex__DOT__vx_f_d_reg__DOT__valid__v5) {
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[4U] 
+	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v5;
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[3U] 
+	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v6;
+	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[2U] 
+	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v7;
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[1U] 
-	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v2;
+	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v8;
 	vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid[0U] 
-	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v3;
+	    = __Vdlyvval__Vortex__DOT__vx_f_d_reg__DOT__valid__v9;
     }
+    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[4U] 
+	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[3U] 
+	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2U] 
+	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] 
 	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
 	[1U];
@@ -197,20 +227,47 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp)
 				        : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__state))
 					    ? vlTOPp->Vortex__DOT__vx_fetch__DOT__JAL_reg
 					    : vlTOPp->Vortex__DOT__vx_fetch__DOT__real_PC)))))));
+    vlTOPp->Vortex__DOT__f_d_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__f_d_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__f_d_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__f_d_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__f_d_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__f_d_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__f_d_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__f_d_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
 	[0U];
+    vlTOPp->Vortex__DOT__decode_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__decode_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__decode_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
@@ -228,10 +285,19 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     VL_SIG8(__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v2,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v3,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v4,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v2,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v3,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v4,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0,0,0);
     VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v2,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v3,0,0);
+    VL_SIG8(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v4,0,0);
     VL_SIG8(__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0,0,0);
     VL_SIG16(__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0);
     VL_SIG16(__Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0,11,0);
@@ -239,16 +305,34 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v2,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v3,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v4,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v2,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v3,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v4,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v2,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v3,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v4,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0,31,0);
-    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v2,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v3,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v4,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0,31,0);
     VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v2,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v3,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v4,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v2,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v3,31,0);
+    VL_SIG(__Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v4,31,0);
     // Body
     __Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0 = 0U;
     __Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0 = 0U;
@@ -256,37 +340,50 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     // ALWAYS at VX_m_w_reg.v:60
     __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid
-	[1U];
+	[4U];
     __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid
+	[3U];
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v2 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid
+	[2U];
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v3 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid
+	[1U];
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v4 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid
 	[0U];
     // ALWAYS at VX_e_m_reg.v:126
     __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data
-	[1U];
+	[4U];
     __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data
+	[3U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v2 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data
+	[2U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v3 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data
+	[1U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v4 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data
 	[0U];
     // ALWAYS at VX_e_m_reg.v:126
     __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid
-	[1U];
+	[4U];
     __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid
-	[0U];
-    // ALWAYS at VX_m_w_reg.v:60
-    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result
+	[3U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v2 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid
+	[2U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v3 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid
 	[1U];
-    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result
-	[0U];
-    // ALWAYS at VX_m_w_reg.v:60
-    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result
-	[1U];
-    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v4 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid
 	[0U];
     // ALWAYS at VX_d_e_reg.v:138
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__upper_immed 
@@ -304,6 +401,38 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     // ALWAYS at VX_csr_handler.v:34
     vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address 
 	= vlTOPp->Vortex__DOT__decode_csr_address;
+    // ALWAYS at VX_m_w_reg.v:60
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result
+	[4U];
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result
+	[3U];
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v2 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result
+	[2U];
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v3 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result
+	[1U];
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v4 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result
+	[0U];
+    // ALWAYS at VX_m_w_reg.v:60
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result
+	[4U];
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result
+	[3U];
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v2 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result
+	[2U];
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v3 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result
+	[1U];
+    __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v4 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result
+	[0U];
     // ALWAYS at VX_csr_handler.v:34
     vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle 
 	= (VL_ULL(1) + vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle);
@@ -319,22 +448,30 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 			       | (0x23U == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))
 			       ? 1U : 0U))));
     // ALWAYS at VX_e_m_reg.v:126
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
-	[1U];
-    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
-	[0U];
-    // ALWAYS at VX_e_m_reg.v:126
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type;
     // ALWAYS at VX_d_e_reg.v:138
     __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z
+	   [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid
+	   [4U]);
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z
+	   [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid
+	   [3U]);
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v2 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z
+	   [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid
+	   [2U]);
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v3 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z
 	   [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid
 	   [1U]);
-    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1 
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v4 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z
 	   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid
@@ -350,12 +487,28 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     // ALWAYS at VX_e_m_reg.v:126
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC;
     // ALWAYS at VX_e_m_reg.v:126
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed;
+    // ALWAYS at VX_e_m_reg.v:126
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest 
 	= (vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 	   [0U] + vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset);
     // ALWAYS at VX_e_m_reg.v:126
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
-	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed;
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
+	[4U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
+	[3U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v2 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
+	[2U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v3 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
+	[1U];
+    __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v4 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result
+	[0U];
     // ALWAYS at VX_m_w_reg.v:60
     vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     // ALWAYS at VX_register_file.v:36
@@ -388,11 +541,26 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     }
     // ALWAYS at VX_d_e_reg.v:138
     __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
+	   [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data
+	   [4U]);
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
+	   [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data
+	   [3U]);
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v2 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
+	   [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data
+	   [2U]);
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v3 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
 	   [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data
 	   [1U]);
-    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1 
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v4 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
 	   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data
@@ -407,50 +575,107 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     }
     // ALWAYS at VX_d_e_reg.v:138
     __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
+	   [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data
+	   [4U]);
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
+	   [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data
+	   [3U]);
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v2 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
+	   [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data
+	   [2U]);
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v3 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
 	   [1U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data
 	   [1U]);
-    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1 
+    __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v4 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z
 	   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data
 	   [0U]);
     // ALWAYSPOST at VX_m_w_reg.v:69
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[1U] 
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[4U] 
 	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v0;
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[0U] 
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[3U] 
 	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v1;
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[2U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v2;
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[1U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v3;
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid[0U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__valid__v4;
     // ALWAYSPOST at VX_e_m_reg.v:137
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[1U] 
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[4U] 
 	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v0;
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[0U] 
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[3U] 
 	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v1;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[2U] 
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v2;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[1U] 
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v3;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[0U] 
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__b_reg_data__v4;
     // ALWAYSPOST at VX_e_m_reg.v:146
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] 
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[4U] 
 	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v0;
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] 
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[3U] 
 	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v1;
-    // ALWAYSPOST at VX_m_w_reg.v:62
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[1U] 
-	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0;
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[0U] 
-	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[2U] 
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v2;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] 
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v3;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[0U] 
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__valid__v4;
     // ALWAYSPOST at VX_m_w_reg.v:63
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[1U] 
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[4U] 
 	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v0;
-    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[0U] 
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[3U] 
 	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v1;
-    // ALWAYSPOST at VX_e_m_reg.v:128
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] 
-	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0;
-    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] 
-	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1;
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[2U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v2;
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[1U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v3;
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result[0U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__mem_result__v4;
+    // ALWAYSPOST at VX_m_w_reg.v:62
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[4U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v0;
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[3U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v1;
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[2U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v2;
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[1U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v3;
+    vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result[0U] 
+	= __Vdlyvval__Vortex__DOT__vx_m_w_reg__DOT__alu_result__v4;
     // ALWAYSPOST at VX_d_e_reg.v:160
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] 
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[4U] 
 	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v0;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] 
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[3U] 
 	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v1;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[2U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v2;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v3;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[0U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__valid__v4;
+    // ALWAYSPOST at VX_e_m_reg.v:128
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[4U] 
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v0;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[3U] 
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v1;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[2U] 
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v2;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] 
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v3;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[0U] 
+	= __Vdlyvval__Vortex__DOT__vx_e_m_reg__DOT__alu_result__v4;
     // ALWAYSPOST at VX_register_file.v:39
     if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0) {
 	vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers__v0] 
@@ -462,60 +687,120 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	    = __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers__v0;
     }
     // ALWAYSPOST at VX_d_e_reg.v:143
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[1U] 
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[4U] 
 	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v0;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[0U] 
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[3U] 
 	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v1;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v2;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[1U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v3;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[0U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__a_reg_data__v4;
     // ALWAYSPOST at VX_csr_handler.v:45
     if (__Vdlyvset__Vortex__DOT__vx_csr_handler__DOT__csr__v0) {
 	vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr[__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0] 
 	    = __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0;
     }
     // ALWAYSPOST at VX_d_e_reg.v:144
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[1U] 
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[4U] 
 	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v0;
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[0U] 
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[3U] 
 	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v1;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v2;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[1U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v3;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[0U] 
+	= __Vdlyvval__Vortex__DOT__vx_d_e_reg__DOT__b_reg_data__v4;
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[4U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[3U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[4U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[3U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
-	[1U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
-	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[4U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[3U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
+	[2U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
 	[1U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
 	[0U];
     // ALWAYS at VX_d_e_reg.v:138
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	    ? 0U : (IData)(vlTOPp->Vortex__DOT__decode_branch_type));
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[4U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[3U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
 	[1U];
@@ -564,6 +849,13 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__curr_PC = 
 	((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
 	  ? 0U : vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC);
+    vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC 
+					       + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
+						  << 1U));
+    // ALWAYS at VX_d_e_reg.v:138
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
+	    ? 0xdeadbeefU : vlTOPp->Vortex__DOT__decode_itype_immed);
     // ALWAYS at VX_d_e_reg.v:138
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal_offset 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -596,13 +888,21 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 					   >> 0x14U))))
 				 ? 0xb0000000U : 0xdeadbeefU)
 			     : 0xdeadbeefU))));
-    vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC 
-					       + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
-						  << 1U));
-    // ALWAYS at VX_d_e_reg.v:138
-    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed 
-	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
-	    ? 0xdeadbeefU : vlTOPp->Vortex__DOT__decode_itype_immed);
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[2U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[1U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[0U];
     vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data[1U] 
@@ -611,12 +911,27 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[3U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[4U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
     // ALWAYS at VX_e_m_reg.v:126
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
     // ALWAYS at VX_m_w_reg.v:60
     vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd;
     // ALWAYS at VX_m_w_reg.v:60
     vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb;
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data
 	[1U];
@@ -639,40 +954,97 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 		    ? (vlTOPp->Vortex__DOT__csr_decode_csr_data 
 		       & ((IData)(0xffffffffU) - vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__csr_mask))
 		    : 0xdeadbeefU)));
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT__m_w_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__m_w_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__m_w_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT__e_m_b_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__e_m_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__e_m_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__e_m_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__e_m_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT__e_m_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__e_m_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__e_m_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
 	[0U];
-    vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
-	[1U];
-    vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
-	[0U];
+    vlTOPp->Vortex__DOT__m_w_mem_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
+	[4U];
+    vlTOPp->Vortex__DOT__m_w_mem_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
+	[3U];
+    vlTOPp->Vortex__DOT__m_w_mem_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
+	[2U];
     vlTOPp->Vortex__DOT__m_w_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
 	[1U];
     vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
 	[0U];
-    vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
+    vlTOPp->Vortex__DOT__m_w_alu_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT__m_w_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT__m_w_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
+	[2U];
+    vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
 	[1U];
-    vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
+    vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
 	[0U];
+    vlTOPp->Vortex__DOT__d_e_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__d_e_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__d_e_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT__e_m_alu_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT__e_m_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT__e_m_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
+	[2U];
+    vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
+	[1U];
+    vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
+	[0U];
+    vlTOPp->Vortex__DOT__d_e_a_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__d_e_a_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__d_e_a_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__d_e_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__d_e_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
@@ -699,46 +1071,102 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						    : 
 						   vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr
 						   [vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address]))));
+    vlTOPp->Vortex__DOT__d_e_b_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__d_e_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__d_e_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__d_e_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__d_e_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[4U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[3U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[4U] 
+	= vlTOPp->Vortex__DOT__e_m_b_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[3U] 
+	= vlTOPp->Vortex__DOT__e_m_b_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[2U] 
+	= vlTOPp->Vortex__DOT__e_m_b_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] 
 	= vlTOPp->Vortex__DOT__e_m_b_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] 
 	= vlTOPp->Vortex__DOT__e_m_b_reg_data[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__e_m_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__e_m_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__e_m_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__e_m_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__e_m_valid[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[4U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[3U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[0U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[4U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[3U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__e_m_alu_result[1U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__e_m_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[2U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[2U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__d_e_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__d_e_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__d_e_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__d_e_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] 
@@ -746,10 +1174,26 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__execute_branch_stall = ((0U 
 						  != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) 
 						 | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal));
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[2U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[1U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[0U];
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[3U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[4U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     // ALWAYS at VX_d_e_reg.v:138
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -758,6 +1202,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd;
     // ALWAYS at VX_e_m_reg.v:126
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb;
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__d_e_a_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__d_e_a_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__d_e_a_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__d_e_a_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[0U] 
@@ -787,28 +1237,82 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 					     & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))
 		     ? (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__mul_alu)
 		     : (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__temp_final_alu)));
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__d_e_b_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__d_e_b_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__d_e_b_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__d_e_b_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__d_e_b_reg_data[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[4U] 
+	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
+	   [4U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
+		   [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
+		   [4U]));
+    vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[3U] 
+	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
+	   [3U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
+		   [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
+		   [3U]));
+    vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[2U] 
+	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
+	   [2U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
+		   [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
+		   [2U]));
     vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] 
 	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
 	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
@@ -823,11 +1327,20 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
 		   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
 		   [0U]));
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
+	[2U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
 	[1U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
 	[0U];
     // ALWAYS at VX_memory.v:74
     vlTOPp->Vortex__DOT__memory_branch_dir = (1U & 
@@ -875,18 +1388,45 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						       == 
 						       vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 						       [0U])))));
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[2U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[1U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
-	[1U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
-	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
 	[1U];
@@ -903,40 +1443,91 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	    ? vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__itype_immed
 	    : vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
 	   [1U]);
+    vlTOPp->out_cache_driver_in_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
+	[4U];
+    vlTOPp->out_cache_driver_in_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
+	[3U];
+    vlTOPp->out_cache_driver_in_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
+	[2U];
     vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
 	[1U];
     vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
 	[0U];
+    vlTOPp->out_cache_driver_in_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
+	[4U];
+    vlTOPp->out_cache_driver_in_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
+	[3U];
+    vlTOPp->out_cache_driver_in_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
+	[2U];
     vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
 	[1U];
     vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
 	[0U];
+    vlTOPp->Vortex__DOT__memory_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__memory_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__memory_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__memory_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT__writeback_write_data[4U] = 
+	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
+	[4U];
+    vlTOPp->Vortex__DOT__writeback_write_data[3U] = 
+	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
+	[3U];
+    vlTOPp->Vortex__DOT__writeback_write_data[2U] = 
+	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
+	[2U];
     vlTOPp->Vortex__DOT__writeback_write_data[1U] = 
 	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
 	[1U];
     vlTOPp->Vortex__DOT__writeback_write_data[0U] = 
 	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
 	[0U];
-    vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
-	[1U];
-    vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
-	[0U];
-    vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
-	[1U];
-    vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
-	[0U];
+    vlTOPp->Vortex__DOT__execute_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__execute_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__execute_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
 	[0U];
+    vlTOPp->out_cache_driver_in_address[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
+	[4U];
+    vlTOPp->out_cache_driver_in_address[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
+	[3U];
+    vlTOPp->out_cache_driver_in_address[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
+	[2U];
+    vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
+	[1U];
+    vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
+	[0U];
+    vlTOPp->Vortex__DOT__memory_alu_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT__memory_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT__memory_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
+	[2U];
+    vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
+	[1U];
+    vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
+	[0U];
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[3U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[4U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
     // ALWAYS at VX_d_e_reg.v:138
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = (0x1fU 
 						& ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling)
@@ -989,6 +1580,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 						    | (IData)(vlTOPp->Vortex__DOT__vx_decode__DOT__is_csr))
 						    ? 1U
 						    : 0U))));
+    vlTOPp->Vortex__DOT__execute_b_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__execute_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__execute_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__execute_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__execute_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
@@ -1003,28 +1600,67 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 					      vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data
 					      [1U]), 
 		      VL_EXTENDS_QI(64,32, vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2));
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__memory_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__memory_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__memory_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__memory_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__memory_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[4U] 
+	= vlTOPp->Vortex__DOT__writeback_write_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[3U] 
+	= vlTOPp->Vortex__DOT__writeback_write_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[2U] 
+	= vlTOPp->Vortex__DOT__writeback_write_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] 
 	= vlTOPp->Vortex__DOT__writeback_write_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] 
 	= vlTOPp->Vortex__DOT__writeback_write_data
 	[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__memory_alu_result[0U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1U] 
-	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
-    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] 
-	= vlTOPp->Vortex__DOT__memory_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__execute_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__execute_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__execute_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__execute_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__execute_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[2U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[2U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__execute_b_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__execute_b_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__execute_b_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__execute_b_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[0U] 
@@ -1323,24 +1959,93 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp)
 	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result;
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result;
+    vlTOPp->Vortex__DOT__execute_alu_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT__execute_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT__execute_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
+	[2U];
     vlTOPp->Vortex__DOT__execute_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
 	[1U];
     vlTOPp->Vortex__DOT__execute_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[0U];
 }
 
-VL_INLINE_OPT void VVortex::_combo__TOP__3(VVortex__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_combo__TOP__3\n"); );
+VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_sequent__TOP__3\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
+    // ALWAYS at VX_writeback.v:43
+    if (VL_UNLIKELY((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)))) {
+	VL_WRITEF("[%x] WB Data: %x {%x}, to register: %2# [%1# %1#]\n",
+		  32,(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next 
+		      - (IData)(4U)),32,vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
+		  [0U],32,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
+		  [0U],5,vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd,
+		  1,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid
+		  [0U],1,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid
+		  [1U]);
+    }
+    // ALWAYS at VX_register_file.v:43
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0x14U))];
+    // ALWAYS at VX_register_file.v:43
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0x14U))];
+    // ALWAYS at VX_register_file.v:43
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0xfU))];
+    // ALWAYS at VX_register_file.v:43
+    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers
+	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
+		   >> 0xfU))];
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data;
+    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] 
+	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data;
+}
+
+VL_INLINE_OPT void VVortex::_combo__TOP__4(VVortex__Syms* __restrict vlSymsp) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_combo__TOP__4\n"); );
+    VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
+    // Body
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[4U] 
+	= vlTOPp->in_cache_driver_out_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[3U] 
+	= vlTOPp->in_cache_driver_out_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2U] 
+	= vlTOPp->in_cache_driver_out_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] 
 	= vlTOPp->in_cache_driver_out_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] 
@@ -1352,6 +2057,15 @@ VL_INLINE_OPT void VVortex::_combo__TOP__3(VVortex__Syms* __restrict vlSymsp) {
 		  32,vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
 		  [0U]);
     }
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
 	[1U];
@@ -1366,28 +2080,61 @@ VL_INLINE_OPT void VVortex::_combo__TOP__3(VVortex__Syms* __restrict vlSymsp) {
 		  [0U],32,vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 		  [0U]);
     }
+    vlTOPp->Vortex__DOT__memory_mem_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
+	[4U];
+    vlTOPp->Vortex__DOT__memory_mem_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
+	[3U];
+    vlTOPp->Vortex__DOT__memory_mem_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
+	[2U];
     vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
 	[1U];
     vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[4U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[3U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[0U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[4U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[3U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[0U];
 }
 
-void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_settle__TOP__4\n"); );
+void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) {
+    VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_settle__TOP__5\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[4U] 
+	= vlTOPp->in_cache_driver_out_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[3U] 
+	= vlTOPp->in_cache_driver_out_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2U] 
+	= vlTOPp->in_cache_driver_out_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[1U] 
 	= vlTOPp->in_cache_driver_out_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[0U] 
 	= vlTOPp->in_cache_driver_out_data[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[4U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[3U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[1U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__valid
 	[1U];
@@ -1402,18 +2149,45 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data;
     vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] 
 	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data;
+    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[4U] 
+	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[3U] 
+	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2U] 
+	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[1U] 
 	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[4U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[3U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[1U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result
 	[1U];
@@ -1502,24 +2276,57 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) {
 		  32,vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
 		  [0U]);
     }
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data
 	[0U];
+    vlTOPp->Vortex__DOT__m_w_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__m_w_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__m_w_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__m_w_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__m_w_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT__f_d_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__f_d_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__f_d_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__f_d_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__f_d_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_f_d_reg__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT__m_w_alu_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT__m_w_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT__m_w_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
+	[2U];
     vlTOPp->Vortex__DOT__m_w_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
 	[1U];
     vlTOPp->Vortex__DOT__m_w_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result
 	[0U];
+    vlTOPp->Vortex__DOT__m_w_mem_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
+	[4U];
+    vlTOPp->Vortex__DOT__m_w_mem_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
+	[3U];
+    vlTOPp->Vortex__DOT__m_w_mem_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
+	[2U];
     vlTOPp->Vortex__DOT__m_w_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
 	[1U];
     vlTOPp->Vortex__DOT__m_w_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result
@@ -1740,116 +2547,158 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) {
 							  >> 0x19U)))
 						      ? 0U
 						      : 1U))))))))));
+    vlTOPp->Vortex__DOT__memory_mem_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
+	[4U];
+    vlTOPp->Vortex__DOT__memory_mem_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
+	[3U];
+    vlTOPp->Vortex__DOT__memory_mem_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
+	[2U];
     vlTOPp->Vortex__DOT__memory_mem_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
 	[1U];
     vlTOPp->Vortex__DOT__memory_mem_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_mem_result
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[4U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[3U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[1U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[0U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__m_w_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__m_w_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__f_d_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__f_d_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__f_d_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__f_d_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__f_d_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__m_w_alu_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__m_w_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__m_w_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[4U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[3U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[1U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[0U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[4U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[3U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2U] 
+	= vlTOPp->Vortex__DOT__m_w_mem_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[1U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[0U] 
 	= vlTOPp->Vortex__DOT__m_w_mem_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[4U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[3U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[1U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[0U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[4U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[3U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2U] 
+	= vlTOPp->Vortex__DOT__memory_mem_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[1U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[0U] 
 	= vlTOPp->Vortex__DOT__memory_mem_result[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_valid
 	[0U];
+    vlTOPp->Vortex__DOT__decode_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__decode_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__decode_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__decode_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__decode_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__decode_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__decode_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__decode_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__decode_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__decode_valid[0U];
 }
 
-VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_sequent__TOP__5\n"); );
-    VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    // ALWAYS at VX_writeback.v:43
-    if (VL_UNLIKELY((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)))) {
-	VL_WRITEF("[%x] WB Data: %x {%x}, to register: %2# [%1# %1#]\n",
-		  32,(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next 
-		      - (IData)(4U)),32,vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
-		  [0U],32,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
-		  [0U],5,vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd,
-		  1,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid
-		  [0U],1,vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_valid
-		  [1U]);
-    }
-    // ALWAYS at VX_register_file.v:43
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers
-	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-		   >> 0x14U))];
-    // ALWAYS at VX_register_file.v:43
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers
-	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-		   >> 0x14U))];
-    // ALWAYS at VX_register_file.v:43
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers
-	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-		   >> 0xfU))];
-    // ALWAYS at VX_register_file.v:43
-    vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers
-	[(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
-		   >> 0xfU))];
-    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[1U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data;
-    vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register[0U] 
-	= vlTOPp->Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data;
-}
-
 void VVortex::_initial__TOP__6(VVortex__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_initial__TOP__6\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
     // INITIAL at VX_fetch.v:51
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__valid = (0x1dU 
+						 & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__valid = (0x1bU 
+						 & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__valid = (0x17U 
+						 & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid));
+    vlTOPp->Vortex__DOT__vx_fetch__DOT__valid = (0xfU 
+						 & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid));
     vlTOPp->Vortex__DOT__vx_fetch__DOT__valid = (1U 
 						 | (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid));
-    vlTOPp->Vortex__DOT__vx_fetch__DOT__valid = (1U 
-						 & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid));
     vlTOPp->Vortex__DOT__vx_fetch__DOT__stall_reg = 0U;
     vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg = 0U;
     vlTOPp->Vortex__DOT__vx_fetch__DOT__old = 0U;
@@ -1888,6 +2737,18 @@ void VVortex::_initial__TOP__6(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[1U] = 0U;
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[1U] = 0U;
     vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[1U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[2U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[2U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[2U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[2U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[3U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[3U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[3U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[3U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[4U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[4U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid[4U] = 0U;
+    vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result[4U] = 0U;
     // INITIAL at VX_d_e_reg.v:82
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[0U] = 0U;
@@ -1900,6 +2761,21 @@ void VVortex::_initial__TOP__6(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[1U] = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[1U] = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[1U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[2U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[2U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[3U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[3U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[3U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[3U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[3U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[4U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[4U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid[4U] = 0U;
+    vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid_z[4U] = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb = 0U;
     vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out = 0U;
@@ -1921,6 +2797,12 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_sequent__TOP__7\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__decode_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__decode_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__decode_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__decode_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[0U] 
@@ -2324,10 +3206,34 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__7(VVortex__Syms* __restrict vlSymsp)
 	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
 		 & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) 
 		    >> 1U)));
+    vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[2U] 
+	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
+		 & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) 
+		    >> 2U)));
+    vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[3U] 
+	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
+		 & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) 
+		    >> 3U)));
+    vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[4U] 
+	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
+		 & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) 
+		    >> 4U)));
+    vlTOPp->Vortex__DOT__fetch_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__fetch_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__fetch_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__fetch_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__fetch_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__fetch_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__fetch_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[0U] 
@@ -2367,6 +3273,12 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[1U] 
 	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[3U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[4U] 
+	= vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U 
 						 == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address))
 						 ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle)
@@ -2394,18 +3306,45 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__memory_branch_dest = (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__curr_PC 
 					       + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset 
 						  << 1U));
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__b_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[4U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[3U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[1U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result
 	[1U];
@@ -2416,21 +3355,54 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[1U] 
 	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[3U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[4U] 
+	= vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next;
     vlTOPp->Vortex__DOT__execute_branch_stall = ((0U 
 						  != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type)) 
 						 | (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__jal));
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[4U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[3U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[1U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__a_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__b_reg_data
 	[1U];
@@ -2441,6 +3413,12 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[1U] 
 	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[3U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
+    vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[4U] 
+	= vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out;
     vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd 
 	= ((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 		       >> 0x14U)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) 
@@ -2451,6 +3429,27 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 		       >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) 
 	    & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 			       >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb)));
+    vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[4U] 
+	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
+	   [4U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
+		   [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
+		   [4U]));
+    vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[3U] 
+	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
+	   [3U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
+		   [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
+		   [3U]));
+    vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[2U] 
+	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
+	   [2U] : ((1U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
+		   [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
+		   [2U]));
     vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data[1U] 
 	= ((3U == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
 	    ? vlTOPp->Vortex__DOT__vx_writeback__DOT__out_pc_data
@@ -2465,26 +3464,62 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 		    ? vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_alu_result
 		   [0U] : vlTOPp->Vortex__DOT____Vcellinp__vx_writeback__in_mem_result
 		   [0U]));
+    vlTOPp->Vortex__DOT__e_m_b_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__e_m_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__e_m_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__e_m_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__e_m_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT__e_m_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__e_m_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__e_m_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__e_m_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__e_m_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT__e_m_alu_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT__e_m_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT__e_m_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
+	[2U];
     vlTOPp->Vortex__DOT__e_m_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
 	[1U];
     vlTOPp->Vortex__DOT__e_m_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result
 	[0U];
+    vlTOPp->Vortex__DOT__d_e_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__d_e_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__d_e_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__d_e_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__d_e_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT__d_e_a_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__d_e_a_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__d_e_a_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__d_e_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__d_e_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT__d_e_b_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__d_e_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__d_e_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__d_e_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__d_e_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data
@@ -2502,32 +3537,77 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	     & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction 
 				>> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) 
 	   & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)));
+    vlTOPp->Vortex__DOT__writeback_write_data[4U] = 
+	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
+	[4U];
+    vlTOPp->Vortex__DOT__writeback_write_data[3U] = 
+	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
+	[3U];
+    vlTOPp->Vortex__DOT__writeback_write_data[2U] = 
+	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
+	[2U];
     vlTOPp->Vortex__DOT__writeback_write_data[1U] = 
 	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
 	[1U];
     vlTOPp->Vortex__DOT__writeback_write_data[0U] = 
 	vlTOPp->Vortex__DOT____Vcellout__vx_writeback__out_write_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[4U] 
+	= vlTOPp->Vortex__DOT__e_m_b_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[3U] 
+	= vlTOPp->Vortex__DOT__e_m_b_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[2U] 
+	= vlTOPp->Vortex__DOT__e_m_b_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[1U] 
 	= vlTOPp->Vortex__DOT__e_m_b_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2[0U] 
 	= vlTOPp->Vortex__DOT__e_m_b_reg_data[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__e_m_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__e_m_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__e_m_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__e_m_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__e_m_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__e_m_alu_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__e_m_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__e_m_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__d_e_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__d_e_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__d_e_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__d_e_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__d_e_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__d_e_a_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__d_e_a_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__d_e_a_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__d_e_a_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__d_e_a_reg_data[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__d_e_b_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__d_e_b_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__d_e_b_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__d_e_b_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[0U] 
@@ -2556,24 +3636,60 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						!= (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) 
 	    & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) 
 	   & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)));
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[4U] 
+	= vlTOPp->Vortex__DOT__writeback_write_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[3U] 
+	= vlTOPp->Vortex__DOT__writeback_write_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[2U] 
+	= vlTOPp->Vortex__DOT__writeback_write_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[1U] 
 	= vlTOPp->Vortex__DOT__writeback_write_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_write_data[0U] 
 	= vlTOPp->Vortex__DOT__writeback_write_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_rd2
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_valid
 	[1U];
@@ -2588,12 +3704,6 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 		  [0U],32,vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 		  [0U]);
     }
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-	[1U];
-    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] 
-	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
-	[0U];
     // ALWAYS at VX_memory.v:74
     vlTOPp->Vortex__DOT__memory_branch_dir = (1U & 
 					      ((4U 
@@ -2640,18 +3750,60 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						       == 
 						       vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 						       [0U])))));
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[2U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[1U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[1U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[0U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_memory__in_alu_result
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
 	[1U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid[0U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_valid
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data
 	[1U];
@@ -2692,22 +3844,36 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
     vlTOPp->Vortex__DOT__forwarding_src1_fwd = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) 
 						 | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)) 
 						| (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd));
+    vlTOPp->out_cache_driver_in_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
+	[4U];
+    vlTOPp->out_cache_driver_in_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
+	[3U];
+    vlTOPp->out_cache_driver_in_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
+	[2U];
     vlTOPp->out_cache_driver_in_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
 	[1U];
     vlTOPp->out_cache_driver_in_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data
 	[0U];
+    vlTOPp->out_cache_driver_in_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
+	[4U];
+    vlTOPp->out_cache_driver_in_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
+	[3U];
+    vlTOPp->out_cache_driver_in_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
+	[2U];
     vlTOPp->out_cache_driver_in_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
 	[1U];
     vlTOPp->out_cache_driver_in_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid
 	[0U];
+    vlTOPp->Vortex__DOT__memory_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__memory_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__memory_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__memory_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__memory_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_valid
 	[0U];
-    vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
-	[1U];
-    vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
-	[0U];
     // ALWAYS at VX_fetch.v:113
     vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC = (
 						   ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) 
@@ -2718,14 +3884,42 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						     & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg)))
 						     ? vlTOPp->Vortex__DOT__memory_branch_dest
 						     : vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use));
+    vlTOPp->out_cache_driver_in_address[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
+	[4U];
+    vlTOPp->out_cache_driver_in_address[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
+	[3U];
+    vlTOPp->out_cache_driver_in_address[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
+	[2U];
+    vlTOPp->out_cache_driver_in_address[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
+	[1U];
+    vlTOPp->out_cache_driver_in_address[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address
+	[0U];
+    vlTOPp->Vortex__DOT__memory_alu_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT__memory_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT__memory_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
+	[2U];
     vlTOPp->Vortex__DOT__memory_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
 	[1U];
     vlTOPp->Vortex__DOT__memory_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_memory__out_alu_result
 	[0U];
+    vlTOPp->Vortex__DOT__execute_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__execute_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__execute_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__execute_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__execute_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_valid
 	[0U];
+    vlTOPp->Vortex__DOT__execute_b_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__execute_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__execute_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__execute_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__execute_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_b_reg_data
@@ -2747,23 +3941,65 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
 		 & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) 
 		    >> 1U)));
+    vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[2U] 
+	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
+		 & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) 
+		    >> 2U)));
+    vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[3U] 
+	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
+		 & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) 
+		    >> 3U)));
+    vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid[4U] 
+	= (1U & ((~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)) 
+		 & ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__valid) 
+		    >> 4U)));
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__memory_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__memory_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__memory_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__memory_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__memory_valid[0U];
     vlTOPp->curr_PC = vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC;
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__memory_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__memory_alu_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__memory_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__memory_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__execute_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__execute_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__execute_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__execute_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__execute_valid[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__execute_b_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__execute_b_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__execute_b_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__execute_b_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[0U] 
@@ -3058,6 +4294,12 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						  [1U] 
 						  + vlTOPp->Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2)))));
     }
+    vlTOPp->Vortex__DOT__fetch_valid[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
+	[4U];
+    vlTOPp->Vortex__DOT__fetch_valid[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
+	[3U];
+    vlTOPp->Vortex__DOT__fetch_valid[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
+	[2U];
     vlTOPp->Vortex__DOT__fetch_valid[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
 	[1U];
     vlTOPp->Vortex__DOT__fetch_valid[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_fetch__out_valid
@@ -3066,22 +4308,130 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result;
     vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result;
+    vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[4U] 
+	= vlTOPp->Vortex__DOT__fetch_valid[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[3U] 
+	= vlTOPp->Vortex__DOT__fetch_valid[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2U] 
+	= vlTOPp->Vortex__DOT__fetch_valid[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[1U] 
 	= vlTOPp->Vortex__DOT__fetch_valid[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[0U] 
 	= vlTOPp->Vortex__DOT__fetch_valid[0U];
+    vlTOPp->Vortex__DOT__execute_alu_result[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
+	[4U];
+    vlTOPp->Vortex__DOT__execute_alu_result[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
+	[3U];
+    vlTOPp->Vortex__DOT__execute_alu_result[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
+	[2U];
     vlTOPp->Vortex__DOT__execute_alu_result[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
 	[1U];
     vlTOPp->Vortex__DOT__execute_alu_result[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_execute__out_alu_result
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[4U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[3U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2U] 
+	= vlTOPp->Vortex__DOT__execute_alu_result[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[1U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[0U] 
 	= vlTOPp->Vortex__DOT__execute_alu_result[0U];
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[4U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [4U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [4U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [4U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [4U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [4U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [4U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [4U])));
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[3U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [3U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [3U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [3U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [3U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [3U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [3U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [3U])));
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [2U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [2U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [2U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [2U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [2U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [2U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [2U])));
     vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
 	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
@@ -3138,6 +4488,90 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						   [0U]))
 					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
 					      [0U])));
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[4U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [4U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [4U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [4U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [4U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [4U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [4U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [4U])));
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[3U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [3U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [3U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [3U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [3U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [3U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [3U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [3U])));
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [2U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [2U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [2U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [2U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [2U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [2U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [2U])));
     vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
 	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
@@ -3194,24 +4628,60 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 						   [0U]))
 					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
 					      [0U])));
+    vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[4U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
+	[4U];
+    vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[3U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
+	[3U];
+    vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[2U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
+	[2U];
     vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
 	[1U];
     vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
 	[0U];
+    vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[4U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
+	[4U];
+    vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[3U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
+	[3U];
+    vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[2U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
+	[2U];
     vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
 	[1U];
     vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[4U] 
+	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[3U] 
+	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2U] 
+	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[4U] 
+	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[3U] 
+	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2U] 
+	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
 	[1U];
@@ -3228,6 +4698,21 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
 	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
 	   [1U]);
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[2U] 
+	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
+	   [2U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
+	   [2U]);
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[3U] 
+	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
+	   [3U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
+	   [3U]);
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[4U] 
+	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
+	   [4U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
+	   [4U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[0U] 
 	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
 	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
@@ -3242,18 +4727,63 @@ void VVortex::_settle__TOP__8(VVortex__Syms* __restrict vlSymsp) {
 	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
 	       [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
 	       [1U]));
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[2U] 
+	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
+	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
+	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
+	       [2U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
+	       [2U]));
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[3U] 
+	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
+	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
+	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
+	       [3U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
+	       [3U]));
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[4U] 
+	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
+	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
+	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
+	       [4U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
+	       [4U]));
+    vlTOPp->Vortex__DOT__decode_b_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__decode_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__decode_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__decode_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__decode_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT__decode_a_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__decode_a_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__decode_a_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__decode_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__decode_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__decode_b_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__decode_b_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__decode_b_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__decode_b_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__decode_b_reg_data[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__decode_a_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__decode_a_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__decode_a_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__decode_a_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[0U] 
@@ -3264,6 +4794,90 @@ VL_INLINE_OPT void VVortex::_combo__TOP__9(VVortex__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_combo__TOP__9\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[4U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [4U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [4U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [4U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [4U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [4U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [4U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [4U])));
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[3U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [3U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [3U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [3U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [3U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [3U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [3U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [3U])));
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [2U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [2U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [2U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [2U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [2U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [2U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [2U])));
     vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[1U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)
 	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
@@ -3320,6 +4934,90 @@ VL_INLINE_OPT void VVortex::_combo__TOP__9(VVortex__Syms* __restrict vlSymsp) {
 						   [0U]))
 					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
 					      [0U])));
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[4U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [4U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [4U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [4U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [4U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [4U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [4U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [4U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [4U])));
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[3U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [3U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [3U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [3U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [3U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [3U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [3U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [3U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [3U])));
+    vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2U] 
+	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
+	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
+	        ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next
+	       [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+	       [2U]) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd)
+			 ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+			     ? vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next
+			    [2U] : ((2U == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))
+				     ? vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data
+				    [2U] : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result
+				    [2U])) : ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd)
+					       ? ((3U 
+						   == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						   ? 
+						  vlTOPp->Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next
+						  [2U]
+						   : 
+						  ((2U 
+						    == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))
+						    ? 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data
+						   [2U]
+						    : 
+						   vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result
+						   [2U]))
+					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
+					      [2U])));
     vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[1U] 
 	= ((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd)
 	    ? ((3U == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))
@@ -3376,24 +5074,60 @@ VL_INLINE_OPT void VVortex::_combo__TOP__9(VVortex__Syms* __restrict vlSymsp) {
 						   [0U]))
 					       : vlTOPp->Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result
 					      [0U])));
+    vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[4U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
+	[4U];
+    vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[3U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
+	[3U];
+    vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[2U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
+	[2U];
     vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
 	[1U];
     vlTOPp->Vortex__DOT__forwarding_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data
 	[0U];
+    vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[4U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
+	[4U];
+    vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[3U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
+	[3U];
+    vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[2U] 
+	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
+	[2U];
     vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
 	[1U];
     vlTOPp->Vortex__DOT__forwarding_src1_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[4U] 
+	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[3U] 
+	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2U] 
+	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
 	[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[0U] 
 	= vlTOPp->Vortex__DOT__forwarding_src2_fwd_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[4U] 
+	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
+	[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[3U] 
+	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
+	[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2U] 
+	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
+	[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[1U] 
 	= vlTOPp->Vortex__DOT__forwarding_src1_fwd_data
 	[1U];
@@ -3410,6 +5144,21 @@ VL_INLINE_OPT void VVortex::_combo__TOP__9(VVortex__Syms* __restrict vlSymsp) {
 	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
 	   [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
 	   [1U]);
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[2U] 
+	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
+	   [2U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
+	   [2U]);
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[3U] 
+	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
+	   [3U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
+	   [3U]);
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[4U] 
+	= ((IData)(vlTOPp->Vortex__DOT__forwarding_src2_fwd)
+	    ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data
+	   [4U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register
+	   [4U]);
     vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[0U] 
 	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
 	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
@@ -3424,18 +5173,63 @@ VL_INLINE_OPT void VVortex::_combo__TOP__9(VVortex__Syms* __restrict vlSymsp) {
 	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
 	       [1U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
 	       [1U]));
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[2U] 
+	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
+	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
+	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
+	       [2U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
+	       [2U]));
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[3U] 
+	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
+	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
+	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
+	       [3U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
+	       [3U]));
+    vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[4U] 
+	= ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction))
+	    ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC
+	    : ((IData)(vlTOPp->Vortex__DOT__forwarding_src1_fwd)
+	        ? vlTOPp->Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data
+	       [4U] : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register
+	       [4U]));
+    vlTOPp->Vortex__DOT__decode_b_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__decode_b_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__decode_b_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__decode_b_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__decode_b_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_b_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT__decode_a_reg_data[4U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
+	[4U];
+    vlTOPp->Vortex__DOT__decode_a_reg_data[3U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
+	[3U];
+    vlTOPp->Vortex__DOT__decode_a_reg_data[2U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
+	[2U];
     vlTOPp->Vortex__DOT__decode_a_reg_data[1U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
 	[1U];
     vlTOPp->Vortex__DOT__decode_a_reg_data[0U] = vlTOPp->Vortex__DOT____Vcellout__vx_decode__out_a_reg_data
 	[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__decode_b_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__decode_b_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__decode_b_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__decode_b_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[0U] 
 	= vlTOPp->Vortex__DOT__decode_b_reg_data[0U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[4U] 
+	= vlTOPp->Vortex__DOT__decode_a_reg_data[4U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[3U] 
+	= vlTOPp->Vortex__DOT__decode_a_reg_data[3U];
+    vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[2U] 
+	= vlTOPp->Vortex__DOT__decode_a_reg_data[2U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[1U] 
 	= vlTOPp->Vortex__DOT__decode_a_reg_data[1U];
     vlTOPp->Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[0U] 
@@ -3453,10 +5247,10 @@ void VVortex::_eval(VVortex__Syms* __restrict vlSymsp) {
     if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) {
 	vlTOPp->_sequent__TOP__2(vlSymsp);
     }
-    vlTOPp->_combo__TOP__3(vlSymsp);
     if (((~ (IData)(vlTOPp->clk)) & (IData)(vlTOPp->__Vclklast__TOP__clk))) {
-	vlTOPp->_sequent__TOP__5(vlSymsp);
+	vlTOPp->_sequent__TOP__3(vlSymsp);
     }
+    vlTOPp->_combo__TOP__4(vlSymsp);
     if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) 
 	 | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) {
 	vlTOPp->_sequent__TOP__7(vlSymsp);
@@ -3487,7 +5281,7 @@ void VVortex::_eval_settle(VVortex__Syms* __restrict vlSymsp) {
     VL_DEBUG_IF(VL_DBG_MSGF("+    VVortex::_eval_settle\n"); );
     VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
     // Body
-    vlTOPp->_settle__TOP__4(vlSymsp);
+    vlTOPp->_settle__TOP__5(vlSymsp);
     vlTOPp->_settle__TOP__8(vlSymsp);
 }
 
@@ -3517,266 +5311,266 @@ void VVortex::_ctor_var_reset() {
     clk = VL_RAND_RESET_I(1);
     reset = VL_RAND_RESET_I(1);
     fe_instruction = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     curr_PC = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32);
     }}
     out_cache_driver_in_mem_read = VL_RAND_RESET_I(3);
     out_cache_driver_in_mem_write = VL_RAND_RESET_I(3);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__fetch_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__f_d_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
     Vortex__DOT__decode_csr_address = VL_RAND_RESET_I(12);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__decode_a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__decode_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__decode_itype_immed = VL_RAND_RESET_I(32);
     Vortex__DOT__decode_branch_type = VL_RAND_RESET_I(3);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__decode_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__d_e_a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__d_e_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__d_e_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
     Vortex__DOT__execute_branch_stall = VL_RAND_RESET_I(1);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__execute_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__execute_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__execute_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__e_m_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__e_m_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__e_m_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
     Vortex__DOT__memory_branch_dir = VL_RAND_RESET_I(1);
     Vortex__DOT__memory_branch_dest = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__memory_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__memory_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__memory_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__m_w_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__m_w_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__m_w_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__writeback_write_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__csr_decode_csr_data = VL_RAND_RESET_I(32);
     Vortex__DOT__forwarding_fwd_stall = VL_RAND_RESET_I(1);
     Vortex__DOT__forwarding_src1_fwd = VL_RAND_RESET_I(1);
     Vortex__DOT__forwarding_src2_fwd = VL_RAND_RESET_I(1);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__forwarding_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__forwarding_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_fetch__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_decode__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_decode__in_write_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_decode__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_execute__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_execute__out_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_execute__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_memory__out_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_memory__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_memory__in_rd2[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_memory__in_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_writeback__out_write_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_writeback__in_valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_fetch__DOT__stall_reg = VL_RAND_RESET_I(1);
@@ -3790,16 +5584,16 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_fetch__DOT__PC_to_use = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_fetch__DOT__stall = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_fetch__DOT__temp_PC = VL_RAND_RESET_I(32);
-    Vortex__DOT__vx_fetch__DOT__valid = VL_RAND_RESET_I(2);
+    Vortex__DOT__vx_fetch__DOT__valid = VL_RAND_RESET_I(5);
     Vortex__DOT__vx_f_d_reg__DOT__instruction = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_f_d_reg__DOT__curr_PC = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_f_d_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_decode__DOT__rd1_register[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_decode__DOT__rd2_register[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_decode__DOT__is_itype = VL_RAND_RESET_I(1);
@@ -3818,10 +5612,10 @@ void VVortex::_ctor_var_reset() {
 	    Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_d_e_reg__DOT__rd = VL_RAND_RESET_I(5);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_d_e_reg__DOT__alu_op = VL_RAND_RESET_I(5);
@@ -3839,13 +5633,13 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_d_e_reg__DOT__curr_PC = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_d_e_reg__DOT__jal = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_d_e_reg__DOT__jal_offset = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_d_e_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_d_e_reg__DOT__valid_z[__Vi0] = VL_RAND_RESET_I(1);
     }}
     Vortex__DOT__vx_d_e_reg__DOT__stalling = VL_RAND_RESET_I(1);
@@ -3855,14 +5649,14 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_execute__DOT__vx_alu_0__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
     Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__ALU_in2 = VL_RAND_RESET_I(32);
     Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result = VL_RAND_RESET_Q(64);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_e_m_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_e_m_reg__DOT__rd = VL_RAND_RESET_I(5);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_e_m_reg__DOT__wb = VL_RAND_RESET_I(2);
@@ -3877,22 +5671,22 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_e_m_reg__DOT__branch_type = VL_RAND_RESET_I(3);
     Vortex__DOT__vx_e_m_reg__DOT__jal = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_e_m_reg__DOT__jal_dest = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_e_m_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_m_w_reg__DOT__alu_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_m_w_reg__DOT__mem_result[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_m_w_reg__DOT__rd = VL_RAND_RESET_I(5);
     Vortex__DOT__vx_m_w_reg__DOT__wb = VL_RAND_RESET_I(2);
     Vortex__DOT__vx_m_w_reg__DOT__PC_next = VL_RAND_RESET_I(32);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_m_w_reg__DOT__valid[__Vi0] = VL_RAND_RESET_I(1);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_writeback__DOT__out_pc_data[__Vi0] = VL_RAND_RESET_I(32);
     }}
     Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd = VL_RAND_RESET_I(1);
@@ -3901,13 +5695,13 @@ void VVortex::_ctor_var_reset() {
     Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd = VL_RAND_RESET_I(1);
     Vortex__DOT__vx_forwarding__DOT__src2_wb_fwd = VL_RAND_RESET_I(1);
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[__Vi0] = VL_RAND_RESET_I(32);
     }}
-    { int __Vi0=0; for (; __Vi0<2; ++__Vi0) {
+    { int __Vi0=0; for (; __Vi0<5; ++__Vi0) {
 	    Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[__Vi0] = VL_RAND_RESET_I(32);
     }}
     { int __Vi0=0; for (; __Vi0<4096; ++__Vi0) {
diff --git a/rtl/obj_dir/VVortex.h b/rtl/obj_dir/VVortex.h
index 5d031d33..7b456d55 100644
--- a/rtl/obj_dir/VVortex.h
+++ b/rtl/obj_dir/VVortex.h
@@ -27,10 +27,10 @@ VL_MODULE(VVortex) {
     VL_OUT8(out_cache_driver_in_mem_write,2,0);
     VL_IN(fe_instruction,31,0);
     VL_OUT(curr_PC,31,0);
-    VL_IN(in_cache_driver_out_data[2],31,0);
-    VL_OUT(out_cache_driver_in_address[2],31,0);
-    VL_OUT8(out_cache_driver_in_valid[2],0,0);
-    VL_OUT(out_cache_driver_in_data[2],31,0);
+    VL_IN(in_cache_driver_out_data[5],31,0);
+    VL_OUT(out_cache_driver_in_address[5],31,0);
+    VL_OUT8(out_cache_driver_in_valid[5],0,0);
+    VL_OUT(out_cache_driver_in_data[5],31,0);
     
     // LOCAL SIGNALS
     // Internals; generally not touched by application code
@@ -48,7 +48,7 @@ VL_MODULE(VVortex) {
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__state,4,0);
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__prev_debug,0,0);
 	VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
-	VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,1,0);
+	VL_SIG8(Vortex__DOT__vx_fetch__DOT__valid,4,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
 	VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
@@ -114,50 +114,50 @@ VL_MODULE(VVortex) {
 	VL_SIG64(Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result,63,0);
 	VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
 	VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
-	VL_SIG8(Vortex__DOT__fetch_valid[2],0,0);
-	VL_SIG8(Vortex__DOT__f_d_valid[2],0,0);
-	VL_SIG(Vortex__DOT__decode_a_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT__decode_b_reg_data[2],31,0);
-	VL_SIG8(Vortex__DOT__decode_valid[2],0,0);
-	VL_SIG(Vortex__DOT__d_e_a_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT__d_e_b_reg_data[2],31,0);
-	VL_SIG8(Vortex__DOT__d_e_valid[2],0,0);
-	VL_SIG(Vortex__DOT__execute_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__execute_b_reg_data[2],31,0);
-	VL_SIG8(Vortex__DOT__execute_valid[2],0,0);
-	VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__e_m_b_reg_data[2],31,0);
-	VL_SIG8(Vortex__DOT__e_m_valid[2],0,0);
-	VL_SIG(Vortex__DOT__memory_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__memory_mem_result[2],31,0);
-	VL_SIG8(Vortex__DOT__memory_valid[2],0,0);
-	VL_SIG(Vortex__DOT__m_w_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__m_w_mem_result[2],31,0);
-	VL_SIG8(Vortex__DOT__m_w_valid[2],0,0);
-	VL_SIG(Vortex__DOT__writeback_write_data[2],31,0);
-	VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0);
-	VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0);
-	VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[2],31,0);
-	VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[2],31,0);
+	VL_SIG8(Vortex__DOT__fetch_valid[5],0,0);
+	VL_SIG8(Vortex__DOT__f_d_valid[5],0,0);
+	VL_SIG(Vortex__DOT__decode_a_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT__decode_b_reg_data[5],31,0);
+	VL_SIG8(Vortex__DOT__decode_valid[5],0,0);
+	VL_SIG(Vortex__DOT__d_e_a_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT__d_e_b_reg_data[5],31,0);
+	VL_SIG8(Vortex__DOT__d_e_valid[5],0,0);
+	VL_SIG(Vortex__DOT__execute_alu_result[5],31,0);
+	VL_SIG(Vortex__DOT__execute_b_reg_data[5],31,0);
+	VL_SIG8(Vortex__DOT__execute_valid[5],0,0);
+	VL_SIG(Vortex__DOT__e_m_alu_result[5],31,0);
+	VL_SIG(Vortex__DOT__e_m_b_reg_data[5],31,0);
+	VL_SIG8(Vortex__DOT__e_m_valid[5],0,0);
+	VL_SIG(Vortex__DOT__memory_alu_result[5],31,0);
+	VL_SIG(Vortex__DOT__memory_mem_result[5],31,0);
+	VL_SIG8(Vortex__DOT__memory_valid[5],0,0);
+	VL_SIG(Vortex__DOT__m_w_alu_result[5],31,0);
+	VL_SIG(Vortex__DOT__m_w_mem_result[5],31,0);
+	VL_SIG8(Vortex__DOT__m_w_valid[5],0,0);
+	VL_SIG(Vortex__DOT__writeback_write_data[5],31,0);
+	VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[5],31,0);
+	VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[5],31,0);
+	VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[5],0,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[5],31,0);
+	VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[5],31,0);
 	VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers[32],31,0);
 	VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers[32],31,0);
-	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2],31,0);
-	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0);
-	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2],31,0);
-	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[2],0,0);
-	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[2],31,0);
-	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[2],0,0);
-	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0);
-	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0);
-	VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[2],0,0);
-	VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0);
-	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0);
-	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0);
-	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2],31,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[5],31,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[5],0,0);
+	VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[5],31,0);
+	VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[5],0,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[5],31,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[5],31,0);
+	VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[5],0,0);
+	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[5],31,0);
+	VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[5],31,0);
+	VL_SIG8(Vortex__DOT__vx_m_w_reg__DOT__valid[5],0,0);
+	VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[5],31,0);
+	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[5],31,0);
+	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[5],31,0);
+	VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[5],31,0);
 	VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
     };
     
@@ -175,64 +175,64 @@ VL_MODULE(VVortex) {
 	VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data,31,0);
 	VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result,31,0);
 	VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result,31,0);
-	VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0);
-	VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0);
-	VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0);
-	VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0);
-	VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0);
-	VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[2],0,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0);
-	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0);
+	VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[5],0,0);
+	VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[5],0,0);
+	VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[5],0,0);
+	VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[5],0,0);
+	VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[5],31,0);
+	VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[5],0,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[5],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[5],31,0);
     };
     struct {
-	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0);
+	VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[5],31,0);
     };
     static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
     
@@ -268,7 +268,7 @@ VL_MODULE(VVortex) {
   private:
     static QData _change_request(VVortex__Syms* __restrict vlSymsp);
   public:
-    static void _combo__TOP__3(VVortex__Syms* __restrict vlSymsp);
+    static void _combo__TOP__4(VVortex__Syms* __restrict vlSymsp);
     static void _combo__TOP__9(VVortex__Syms* __restrict vlSymsp);
   private:
     void _ctor_var_reset();
@@ -284,9 +284,9 @@ VL_MODULE(VVortex) {
     static void _initial__TOP__6(VVortex__Syms* __restrict vlSymsp);
     static void _sequent__TOP__1(VVortex__Syms* __restrict vlSymsp);
     static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp);
-    static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp);
+    static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp);
     static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
-    static void _settle__TOP__4(VVortex__Syms* __restrict vlSymsp);
+    static void _settle__TOP__5(VVortex__Syms* __restrict vlSymsp);
     static void _settle__TOP__8(VVortex__Syms* __restrict vlSymsp);
 } VL_ATTR_ALIGNED(128);
 
diff --git a/rtl/obj_dir/VVortex__ALL.a b/rtl/obj_dir/VVortex__ALL.a
index aca83764..3065c98d 100644
Binary files a/rtl/obj_dir/VVortex__ALL.a and b/rtl/obj_dir/VVortex__ALL.a differ
diff --git a/rtl/obj_dir/VVortex__ALLcls.o b/rtl/obj_dir/VVortex__ALLcls.o
index a543a6ab..01499726 100644
Binary files a/rtl/obj_dir/VVortex__ALLcls.o and b/rtl/obj_dir/VVortex__ALLcls.o differ
diff --git a/rtl/obj_dir/VVortex__verFiles.dat b/rtl/obj_dir/VVortex__verFiles.dat
index d6d4f082..c2ed054e 100644
--- a/rtl/obj_dir/VVortex__verFiles.dat
+++ b/rtl/obj_dir/VVortex__verFiles.dat
@@ -5,22 +5,22 @@ S      2862 12889318286  1553966962           0  1553966962           0 "VX_alu.
 S      1495 12889087229  1553211178           0  1553211178           0 "VX_csr_handler.v"
 S      5040 12889318287  1553995422           0  1553995422           0 "VX_d_e_reg.v"
 S     11888 12889419225  1553995767           0  1553995767           0 "VX_decode.v"
-S      1551 12889419227  1553898607           0  1553898607           0 "VX_define.v"
+S      1532 12889419227  1553998396           0  1553998396           0 "VX_define.v"
 S      4077 12889318289  1553997299           0  1553997299           0 "VX_e_m_reg.v"
 S      4908 12889318290  1553997136           0  1553997136           0 "VX_execute.v"
 S      1382 12889050060  1553673124           0  1553673124           0 "VX_f_d_reg.v"
-S      4048 12889419228  1553932280           0  1553932280           0 "VX_fetch.v"
+S      4042 12889419228  1553998456           0  1553998456           0 "VX_fetch.v"
 S      5632 12889086478  1553672336           0  1553672336           0 "VX_forwarding.v"
 S      1677 12889085814  1553673165           0  1553673165           0 "VX_m_w_reg.v"
 S      3002 12889084513  1553997670           0  1553997670           0 "VX_memory.v"
 S      1003 12889419229  1553930745           0  1553930745           0 "VX_register_file.v"
 S      1173 12889419230  1553930874           0  1553930874           0 "VX_writeback.v"
 S     16452 12889419231  1553997933           0  1553997933           0 "Vortex.v"
-T    183333 12889432530  1553998021           0  1553998021           0 "obj_dir/VVortex.cpp"
-T     14673 12889432529  1553998021           0  1553998021           0 "obj_dir/VVortex.h"
-T      1800 12889432532  1553998021           0  1553998021           0 "obj_dir/VVortex.mk"
-T       530 12889432528  1553998021           0  1553998021           0 "obj_dir/VVortex__Syms.cpp"
-T       717 12889432527  1553998021           0  1553998021           0 "obj_dir/VVortex__Syms.h"
-T       464 12889432533  1553998021           0  1553998021           0 "obj_dir/VVortex__ver.d"
-T         0        0  1553998021           0  1553998021           0 "obj_dir/VVortex__verFiles.dat"
-T      1159 12889432531  1553998021           0  1553998021           0 "obj_dir/VVortex_classes.mk"
+T    276821 12889432530  1553998459           0  1553998459           0 "obj_dir/VVortex.cpp"
+T     14673 12889432529  1553998459           0  1553998459           0 "obj_dir/VVortex.h"
+T      1800 12889432532  1553998459           0  1553998459           0 "obj_dir/VVortex.mk"
+T       530 12889432528  1553998459           0  1553998459           0 "obj_dir/VVortex__Syms.cpp"
+T       717 12889432527  1553998459           0  1553998459           0 "obj_dir/VVortex__Syms.h"
+T       464 12889432533  1553998459           0  1553998459           0 "obj_dir/VVortex__ver.d"
+T         0        0  1553998459           0  1553998459           0 "obj_dir/VVortex__verFiles.dat"
+T      1159 12889432531  1553998459           0  1553998459           0 "obj_dir/VVortex_classes.mk"
diff --git a/rtl/obj_dir/debug.txt b/rtl/obj_dir/debug.txt
index 02fdafad..e55f0191 100644
--- a/rtl/obj_dir/debug.txt
+++ b/rtl/obj_dir/debug.txt
@@ -29418,8 +29418,8 @@ RF: Writing 00000000 to 10
 RF: Writing 800020bc to  1
 ----
 ******
-MEM: data read from cache_driver: ffffffff
 [800000c0] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: ffffffff
 
 ----
 ******
@@ -29470,8 +29470,8 @@ RF: Writing 00000002 to 28
 RF: Writing 800020d4 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [800000d8] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -29527,8 +29527,8 @@ RF: Writing 00000003 to 28
 RF: Writing 800020ec to  1
 ----
 ******
-MEM: data read from cache_driver: fffffff0
 [800000f0] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: fffffff0
 
 ----
 ******
@@ -29579,8 +29579,8 @@ RF: Writing 00000004 to 28
 RF: Writing 80002104 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [80000108] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -29631,8 +29631,8 @@ RF: Writing 00000005 to 28
 RF: Writing 8000211c to  1
 ----
 ******
-MEM: data read from cache_driver: ffffffff
 [80000120] WB Data: 80002003 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: ffffffff
 
 ----
 ******
@@ -29683,8 +29683,8 @@ RF: Writing 00000006 to 28
 RF: Writing 80002134 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [80000138] WB Data: 80002003 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -29735,8 +29735,8 @@ RF: Writing 00000007 to 28
 RF: Writing 8000214c to  1
 ----
 ******
-MEM: data read from cache_driver: fffffff0
 [80000150] WB Data: 80002003 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: fffffff0
 
 ----
 ******
@@ -29787,8 +29787,8 @@ RF: Writing 00000008 to 28
 RF: Writing 80002164 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [80000168] WB Data: 80002003 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -29846,8 +29846,8 @@ RF: Writing 8000217c to  1
 RF: Writing 80002000 to  1
 ----
 ******
-MEM: data read from cache_driver: ffffffff
 [80000184] WB Data: 80001fe0 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: ffffffff
 
 ----
 ******
@@ -29905,8 +29905,8 @@ RF: Writing 80002198 to  1
 RF: Writing 80002000 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [800001a0] WB Data: 80001ffa {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -29971,8 +29971,8 @@ RF: Writing 00000000 to  4
 RF: Writing 800021bc to  1
 ----
 ******
-MEM: data read from cache_driver: fffffff0
 [800001c0] WB Data: 80002001 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: fffffff0
 
 ----
 ******
@@ -30062,8 +30062,8 @@ RF: Writing 00000002 to  5
 RF: Writing 800021bc to  1
 ----
 ******
-MEM: data read from cache_driver: fffffff0
 [800001c0] WB Data: 80002001 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: fffffff0
 
 ----
 ******
@@ -30167,8 +30167,8 @@ RF: Writing 00000000 to  4
 RF: Writing 800021e8 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [800001ec] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -30259,8 +30259,8 @@ RF: Writing 00000002 to  5
 RF: Writing 800021e8 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [800001ec] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -30365,8 +30365,8 @@ RF: Writing 00000000 to  4
 RF: Writing 80002218 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [8000021c] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -30458,8 +30458,8 @@ RF: Writing 00000002 to  5
 RF: Writing 80002218 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [8000021c] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -30565,8 +30565,8 @@ RF: Writing 00000000 to  4
 RF: Writing 8000224c to  1
 ----
 ******
-MEM: data read from cache_driver: fffffff0
 [80000250] WB Data: 80002001 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: fffffff0
 
 ----
 ******
@@ -30644,8 +30644,8 @@ RF: Writing 00000002 to  5
 RF: Writing 8000224c to  1
 ----
 ******
-MEM: data read from cache_driver: fffffff0
 [80000250] WB Data: 80002001 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: fffffff0
 
 ----
 ******
@@ -30744,8 +30744,8 @@ RF: Writing 80002274 to  1
 RF: Writing 80002002 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [8000027c] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -30829,8 +30829,8 @@ RF: Writing 80002274 to  1
 RF: Writing 80002002 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [8000027c] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -30934,8 +30934,8 @@ RF: Writing 80002000 to  1
 ******
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [800002ac] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -31025,8 +31025,8 @@ RF: Writing 80002000 to  1
 ******
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [800002ac] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -31103,8 +31103,8 @@ RF: Writing 00000002 to  5
 RF: Writing 800022c8 to  3
 ----
 ******
-MEM: data read from cache_driver: ffffffff
 [800002cc] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
+MEM: data read from cache_driver: ffffffff
 
 ----
 ******
@@ -31172,8 +31172,8 @@ RF: Writing 00000012 to 28
 RF: Writing 800022e4 to  3
 ----
 ******
-MEM: data read from cache_driver: ffffffff
 [800002e8] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
+MEM: data read from cache_driver: ffffffff
 
 ----
 ******
@@ -31546,8 +31546,8 @@ RF: Writing 00000000 to 10
 RF: Writing 800020bc to  1
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [800000c0] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -31598,8 +31598,8 @@ RF: Writing 00000002 to 28
 RF: Writing 800020d4 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [800000d8] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -31655,8 +31655,8 @@ RF: Writing 00000003 to 28
 RF: Writing 800020ec to  1
 ----
 ******
-MEM: data read from cache_driver: 000000f0
 [800000f0] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000f0
 
 ----
 ******
@@ -31707,8 +31707,8 @@ RF: Writing 00000004 to 28
 RF: Writing 80002104 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [80000108] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -31759,8 +31759,8 @@ RF: Writing 00000005 to 28
 RF: Writing 8000211c to  1
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [80000120] WB Data: 80002003 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -31811,8 +31811,8 @@ RF: Writing 00000006 to 28
 RF: Writing 80002134 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [80000138] WB Data: 80002003 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -31863,8 +31863,8 @@ RF: Writing 00000007 to 28
 RF: Writing 8000214c to  1
 ----
 ******
-MEM: data read from cache_driver: 000000f0
 [80000150] WB Data: 80002003 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000f0
 
 ----
 ******
@@ -31915,8 +31915,8 @@ RF: Writing 00000008 to 28
 RF: Writing 80002164 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [80000168] WB Data: 80002003 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -31974,8 +31974,8 @@ RF: Writing 8000217c to  1
 RF: Writing 80002000 to  1
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [80000184] WB Data: 80001fe0 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -32033,8 +32033,8 @@ RF: Writing 80002198 to  1
 RF: Writing 80002000 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [800001a0] WB Data: 80001ffa {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -32099,8 +32099,8 @@ RF: Writing 00000000 to  4
 RF: Writing 800021bc to  1
 ----
 ******
-MEM: data read from cache_driver: 000000f0
 [800001c0] WB Data: 80002001 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000f0
 
 ----
 ******
@@ -32190,8 +32190,8 @@ RF: Writing 00000002 to  5
 RF: Writing 800021bc to  1
 ----
 ******
-MEM: data read from cache_driver: 000000f0
 [800001c0] WB Data: 80002001 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000f0
 
 ----
 ******
@@ -32295,8 +32295,8 @@ RF: Writing 00000000 to  4
 RF: Writing 800021e8 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [800001ec] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -32387,8 +32387,8 @@ RF: Writing 00000002 to  5
 RF: Writing 800021e8 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [800001ec] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -32493,8 +32493,8 @@ RF: Writing 00000000 to  4
 RF: Writing 80002218 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [8000021c] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -32586,8 +32586,8 @@ RF: Writing 00000002 to  5
 RF: Writing 80002218 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [8000021c] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -32693,8 +32693,8 @@ RF: Writing 00000000 to  4
 RF: Writing 8000224c to  1
 ----
 ******
-MEM: data read from cache_driver: 000000f0
 [80000250] WB Data: 80002001 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000f0
 
 ----
 ******
@@ -32772,8 +32772,8 @@ RF: Writing 00000002 to  5
 RF: Writing 8000224c to  1
 ----
 ******
-MEM: data read from cache_driver: 000000f0
 [80000250] WB Data: 80002001 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000f0
 
 ----
 ******
@@ -32872,8 +32872,8 @@ RF: Writing 80002274 to  1
 RF: Writing 80002002 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [8000027c] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -32957,8 +32957,8 @@ RF: Writing 80002274 to  1
 RF: Writing 80002002 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000000f
 [8000027c] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 0000000f
 
 ----
 ******
@@ -33062,8 +33062,8 @@ RF: Writing 80002000 to  1
 ******
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [800002ac] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -33153,8 +33153,8 @@ RF: Writing 80002000 to  1
 ******
 ----
 ******
-MEM: data read from cache_driver: 00000000
 [800002ac] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 00000000
 
 ----
 ******
@@ -33231,8 +33231,8 @@ RF: Writing 00000002 to  5
 RF: Writing 800022c8 to  3
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [800002cc] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -33300,8 +33300,8 @@ RF: Writing 00000012 to 28
 RF: Writing 800022e4 to  3
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [800002e8] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -33674,8 +33674,8 @@ RF: Writing 00000000 to 10
 RF: Writing 800020bc to  1
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [800000c0] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -33726,8 +33726,8 @@ RF: Writing 00000002 to 28
 RF: Writing 800020d4 to  1
 ----
 ******
-MEM: data read from cache_driver: ffffff00
 [800000d8] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: ffffff00
 
 ----
 ******
@@ -33783,8 +33783,8 @@ RF: Writing 00000003 to 28
 RF: Writing 800020ec to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [800000f0] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -33842,8 +33842,8 @@ RF: Writing 00000004 to 28
 RF: Writing 80002108 to  1
 ----
 ******
-MEM: data read from cache_driver: fffff00f
 [8000010c] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: fffff00f
 
 ----
 ******
@@ -33901,8 +33901,8 @@ RF: Writing 00000005 to 28
 RF: Writing 80002124 to  1
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [80000128] WB Data: 80002006 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -33953,8 +33953,8 @@ RF: Writing 00000006 to 28
 RF: Writing 8000213c to  1
 ----
 ******
-MEM: data read from cache_driver: ffffff00
 [80000140] WB Data: 80002006 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: ffffff00
 
 ----
 ******
@@ -34005,8 +34005,8 @@ RF: Writing 00000007 to 28
 RF: Writing 80002154 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [80000158] WB Data: 80002006 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -34064,8 +34064,8 @@ RF: Writing 00000008 to 28
 RF: Writing 80002170 to  1
 ----
 ******
-MEM: data read from cache_driver: fffff00f
 [80000174] WB Data: 80002006 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: fffff00f
 
 ----
 ******
@@ -34130,8 +34130,8 @@ RF: Writing 8000218c to  1
 RF: Writing 80002000 to  1
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [80000194] WB Data: 80001fe0 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -34189,8 +34189,8 @@ RF: Writing 800021a8 to  1
 RF: Writing 80002000 to  1
 ----
 ******
-MEM: data read from cache_driver: ffffff00
 [800001b0] WB Data: 80001ffb {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: ffffff00
 
 ----
 ******
@@ -34255,8 +34255,8 @@ RF: Writing 00000000 to  4
 RF: Writing 800021cc to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [800001d0] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -34353,8 +34353,8 @@ RF: Writing 00000002 to  5
 RF: Writing 800021cc to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [800001d0] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -34465,8 +34465,8 @@ RF: Writing 00000000 to  4
 RF: Writing 800021fc to  1
 ----
 ******
-MEM: data read from cache_driver: fffff00f
 [80000200] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: fffff00f
 
 ----
 ******
@@ -34564,8 +34564,8 @@ RF: Writing 00000002 to  5
 RF: Writing 800021fc to  1
 ----
 ******
-MEM: data read from cache_driver: fffff00f
 [80000200] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: fffff00f
 
 ----
 ******
@@ -34677,8 +34677,8 @@ RF: Writing 00000000 to  4
 RF: Writing 80002230 to  1
 ----
 ******
-MEM: data read from cache_driver: ffffff00
 [80000234] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: ffffff00
 
 ----
 ******
@@ -34770,8 +34770,8 @@ RF: Writing 00000002 to  5
 RF: Writing 80002230 to  1
 ----
 ******
-MEM: data read from cache_driver: ffffff00
 [80000234] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: ffffff00
 
 ----
 ******
@@ -34877,8 +34877,8 @@ RF: Writing 00000000 to  4
 RF: Writing 80002264 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [80000268] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -34958,8 +34958,8 @@ RF: Writing 00000002 to  5
 RF: Writing 80002264 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [80000268] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -35060,8 +35060,8 @@ RF: Writing 80002290 to  1
 RF: Writing 80002004 to  1
 ----
 ******
-MEM: data read from cache_driver: fffff00f
 [80000298] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: fffff00f
 
 ----
 ******
@@ -35147,8 +35147,8 @@ RF: Writing 80002290 to  1
 RF: Writing 80002004 to  1
 ----
 ******
-MEM: data read from cache_driver: fffff00f
 [80000298] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: fffff00f
 
 ----
 ******
@@ -35254,8 +35254,8 @@ RF: Writing 80002000 to  1
 ******
 ----
 ******
-MEM: data read from cache_driver: ffffff00
 [800002cc] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: ffffff00
 
 ----
 ******
@@ -35345,8 +35345,8 @@ RF: Writing 80002000 to  1
 ******
 ----
 ******
-MEM: data read from cache_driver: ffffff00
 [800002cc] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: ffffff00
 
 ----
 ******
@@ -35423,8 +35423,8 @@ RF: Writing 00000002 to  5
 RF: Writing 800022e8 to  3
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [800002ec] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -35492,8 +35492,8 @@ RF: Writing 00000012 to 28
 RF: Writing 80002304 to  3
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [80000308] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -35866,8 +35866,8 @@ RF: Writing 00000000 to 10
 RF: Writing 800020bc to  1
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [800000c0] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -35918,8 +35918,8 @@ RF: Writing 00000002 to 28
 RF: Writing 800020d4 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000ff00
 [800000d8] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000ff00
 
 ----
 ******
@@ -35977,8 +35977,8 @@ RF: Writing 00000003 to 28
 RF: Writing 800020f0 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [800000f4] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -36036,8 +36036,8 @@ RF: Writing 00000004 to 28
 RF: Writing 8000210c to  1
 ----
 ******
-MEM: data read from cache_driver: 0000f00f
 [80000110] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000f00f
 
 ----
 ******
@@ -36095,8 +36095,8 @@ RF: Writing 00000005 to 28
 RF: Writing 80002128 to  1
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [8000012c] WB Data: 80002006 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -36147,8 +36147,8 @@ RF: Writing 00000006 to 28
 RF: Writing 80002140 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000ff00
 [80000144] WB Data: 80002006 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000ff00
 
 ----
 ******
@@ -36206,8 +36206,8 @@ RF: Writing 00000007 to 28
 RF: Writing 8000215c to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [80000160] WB Data: 80002006 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -36265,8 +36265,8 @@ RF: Writing 00000008 to 28
 RF: Writing 80002178 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000f00f
 [8000017c] WB Data: 80002006 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000f00f
 
 ----
 ******
@@ -36331,8 +36331,8 @@ RF: Writing 80002194 to  1
 RF: Writing 80002000 to  1
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [8000019c] WB Data: 80001fe0 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -36390,8 +36390,8 @@ RF: Writing 800021b0 to  1
 RF: Writing 80002000 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000ff00
 [800001b8] WB Data: 80001ffb {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000ff00
 
 ----
 ******
@@ -36463,8 +36463,8 @@ RF: Writing 00000000 to  4
 RF: Writing 800021d8 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [800001dc] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -36561,8 +36561,8 @@ RF: Writing 00000002 to  5
 RF: Writing 800021d8 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [800001dc] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -36673,8 +36673,8 @@ RF: Writing 00000000 to  4
 RF: Writing 80002208 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000f00f
 [8000020c] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000f00f
 
 ----
 ******
@@ -36772,8 +36772,8 @@ RF: Writing 00000002 to  5
 RF: Writing 80002208 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000f00f
 [8000020c] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000f00f
 
 ----
 ******
@@ -36885,8 +36885,8 @@ RF: Writing 00000000 to  4
 RF: Writing 8000223c to  1
 ----
 ******
-MEM: data read from cache_driver: 0000ff00
 [80000240] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000ff00
 
 ----
 ******
@@ -36985,8 +36985,8 @@ RF: Writing 00000002 to  5
 RF: Writing 8000223c to  1
 ----
 ******
-MEM: data read from cache_driver: 0000ff00
 [80000240] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 0000ff00
 
 ----
 ******
@@ -37099,8 +37099,8 @@ RF: Writing 00000000 to  4
 RF: Writing 80002274 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [80000278] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -37180,8 +37180,8 @@ RF: Writing 00000002 to  5
 RF: Writing 80002274 to  1
 ----
 ******
-MEM: data read from cache_driver: 00000ff0
 [80000278] WB Data: 80002002 {babebabe}, to register:  1 [1 0]
+MEM: data read from cache_driver: 00000ff0
 
 ----
 ******
@@ -37282,8 +37282,8 @@ RF: Writing 800022a0 to  1
 RF: Writing 80002004 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000f00f
 [800002a8] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 0000f00f
 
 ----
 ******
@@ -37369,8 +37369,8 @@ RF: Writing 800022a0 to  1
 RF: Writing 80002004 to  1
 ----
 ******
-MEM: data read from cache_driver: 0000f00f
 [800002a8] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 0000f00f
 
 ----
 ******
@@ -37476,8 +37476,8 @@ RF: Writing 80002000 to  1
 ******
 ----
 ******
-MEM: data read from cache_driver: 0000ff00
 [800002dc] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 0000ff00
 
 ----
 ******
@@ -37569,8 +37569,8 @@ RF: Writing 80002000 to  1
 ******
 ----
 ******
-MEM: data read from cache_driver: 0000ff00
 [800002dc] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
+MEM: data read from cache_driver: 0000ff00
 
 ----
 ******
@@ -37649,8 +37649,8 @@ RF: Writing 00000002 to  5
 RF: Writing 800022fc to  3
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [80000300] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -37718,8 +37718,8 @@ RF: Writing 00000012 to 28
 RF: Writing 80002318 to  3
 ----
 ******
-MEM: data read from cache_driver: 000000ff
 [8000031c] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
+MEM: data read from cache_driver: 000000ff
 
 ----
 ******
@@ -38598,9 +38598,9 @@ PC: 800000c4 ----> Received: babebabe for addr: 80002000
 ----
 READING - Addr: 80002000 = ff00ff
 ******
+[800000c0] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: 00ff00ff
 PC: 800000c4 ----> Received: 00ff00ff for addr: 80002000
-[800000c0] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002000 = ff00ff
@@ -38661,9 +38661,9 @@ PC: 800000e0 ----> Received: babebabe for addr: 80002004
 ----
 READING - Addr: 80002004 = ff00ff00
 ******
+[800000dc] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: ff00ff00
 PC: 800000e0 ----> Received: ff00ff00 for addr: 80002004
-[800000dc] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002004 = ff00ff00
@@ -38724,9 +38724,9 @@ PC: 800000fc ----> Received: babebabe for addr: 80002008
 ----
 READING - Addr: 80002008 = ff00ff0
 ******
+[800000f8] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: 0ff00ff0
 PC: 800000fc ----> Received: 0ff00ff0 for addr: 80002008
-[800000f8] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002008 = ff00ff0
@@ -38787,9 +38787,9 @@ PC: 80000118 ----> Received: babebabe for addr: 8000200c
 ----
 READING - Addr: 8000200c = f00ff00f
 ******
+[80000114] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: f00ff00f
 PC: 80000118 ----> Received: f00ff00f for addr: 8000200c
-[80000114] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 8000200c = f00ff00f
@@ -38850,9 +38850,9 @@ PC: 80000134 ----> Received: babebabe for addr: 80002000
 ----
 READING - Addr: 80002000 = ff00ff
 ******
+[80000130] WB Data: 8000200c {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: 00ff00ff
 PC: 80000134 ----> Received: 00ff00ff for addr: 80002000
-[80000130] WB Data: 8000200c {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002000 = ff00ff
@@ -38913,9 +38913,9 @@ PC: 80000150 ----> Received: babebabe for addr: 80002004
 ----
 READING - Addr: 80002004 = ff00ff00
 ******
+[8000014c] WB Data: 8000200c {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: ff00ff00
 PC: 80000150 ----> Received: ff00ff00 for addr: 80002004
-[8000014c] WB Data: 8000200c {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002004 = ff00ff00
@@ -38976,9 +38976,9 @@ PC: 8000016c ----> Received: babebabe for addr: 80002008
 ----
 READING - Addr: 80002008 = ff00ff0
 ******
+[80000168] WB Data: 8000200c {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: 0ff00ff0
 PC: 8000016c ----> Received: 0ff00ff0 for addr: 80002008
-[80000168] WB Data: 8000200c {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002008 = ff00ff0
@@ -39039,9 +39039,9 @@ PC: 80000188 ----> Received: babebabe for addr: 8000200c
 ----
 READING - Addr: 8000200c = f00ff00f
 ******
+[80000184] WB Data: 8000200c {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: f00ff00f
 PC: 80000188 ----> Received: f00ff00f for addr: 8000200c
-[80000184] WB Data: 8000200c {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 8000200c = f00ff00f
@@ -39109,9 +39109,9 @@ PC: 800001a8 ----> Received: babebabe for addr: 80002000
 ----
 READING - Addr: 80002000 = ff00ff
 ******
+[800001a4] WB Data: 80001fe0 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: 00ff00ff
 PC: 800001a8 ----> Received: 00ff00ff for addr: 80002000
-[800001a4] WB Data: 80001fe0 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002000 = ff00ff
@@ -39179,9 +39179,9 @@ PC: 800001c8 ----> Received: babebabe for addr: 80002004
 ----
 READING - Addr: 80002004 = ff00ff00
 ******
+[800001c4] WB Data: 80001ffd {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: ff00ff00
 PC: 800001c8 ----> Received: ff00ff00 for addr: 80002004
-[800001c4] WB Data: 80001ffd {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002004 = ff00ff00
@@ -39256,9 +39256,9 @@ PC: 800001ec ----> Received: babebabe for addr: 80002008
 ----
 READING - Addr: 80002008 = ff00ff0
 ******
+[800001e8] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: 0ff00ff0
 PC: 800001ec ----> Received: 0ff00ff0 for addr: 80002008
-[800001e8] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002008 = ff00ff0
@@ -39358,9 +39358,9 @@ PC: 800001ec ----> Received: babebabe for addr: 80002008
 ----
 READING - Addr: 80002008 = ff00ff0
 ******
+[800001e8] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: 0ff00ff0
 PC: 800001ec ----> Received: 0ff00ff0 for addr: 80002008
-[800001e8] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002008 = ff00ff0
@@ -39474,9 +39474,9 @@ PC: 8000021c ----> Received: babebabe for addr: 8000200c
 ----
 READING - Addr: 8000200c = f00ff00f
 ******
+[80000218] WB Data: 80002008 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: f00ff00f
 PC: 8000021c ----> Received: f00ff00f for addr: 8000200c
-[80000218] WB Data: 80002008 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 8000200c = f00ff00f
@@ -39577,9 +39577,9 @@ PC: 8000021c ----> Received: babebabe for addr: 8000200c
 ----
 READING - Addr: 8000200c = f00ff00f
 ******
+[80000218] WB Data: 80002008 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: f00ff00f
 PC: 8000021c ----> Received: f00ff00f for addr: 8000200c
-[80000218] WB Data: 80002008 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 8000200c = f00ff00f
@@ -39694,9 +39694,9 @@ PC: 80000250 ----> Received: babebabe for addr: 80002004
 ----
 READING - Addr: 80002004 = ff00ff00
 ******
+[8000024c] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: ff00ff00
 PC: 80000250 ----> Received: ff00ff00 for addr: 80002004
-[8000024c] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002004 = ff00ff00
@@ -39798,9 +39798,9 @@ PC: 80000250 ----> Received: babebabe for addr: 80002004
 ----
 READING - Addr: 80002004 = ff00ff00
 ******
+[8000024c] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: ff00ff00
 PC: 80000250 ----> Received: ff00ff00 for addr: 80002004
-[8000024c] WB Data: 80002000 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002004 = ff00ff00
@@ -39916,9 +39916,9 @@ PC: 80000288 ----> Received: babebabe for addr: 80002008
 ----
 READING - Addr: 80002008 = ff00ff0
 ******
+[80000284] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: 0ff00ff0
 PC: 80000288 ----> Received: 0ff00ff0 for addr: 80002008
-[80000284] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002008 = ff00ff0
@@ -40001,9 +40001,9 @@ PC: 80000288 ----> Received: babebabe for addr: 80002008
 ----
 READING - Addr: 80002008 = ff00ff0
 ******
+[80000284] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
 MEM: data read from cache_driver: 0ff00ff0
 PC: 80000288 ----> Received: 0ff00ff0 for addr: 80002008
-[80000284] WB Data: 80002004 {babebabe}, to register:  1 [1 0]
 
 ----
 READING - Addr: 80002008 = ff00ff0
@@ -40107,9 +40107,9 @@ PC: 800002b8 ----> Received: babebabe for addr: 8000200c
 ----
 READING - Addr: 8000200c = f00ff00f
 ******
+[800002b4] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
 MEM: data read from cache_driver: f00ff00f
 PC: 800002b8 ----> Received: f00ff00f for addr: 8000200c
-[800002b4] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
 
 ----
 READING - Addr: 8000200c = f00ff00f
@@ -40198,9 +40198,9 @@ PC: 800002b8 ----> Received: babebabe for addr: 8000200c
 ----
 READING - Addr: 8000200c = f00ff00f
 ******
+[800002b4] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
 MEM: data read from cache_driver: f00ff00f
 PC: 800002b8 ----> Received: f00ff00f for addr: 8000200c
-[800002b4] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
 
 ----
 READING - Addr: 8000200c = f00ff00f
@@ -40309,9 +40309,9 @@ PC: 800002ec ----> Received: babebabe for addr: 80002004
 ----
 READING - Addr: 80002004 = ff00ff00
 ******
+[800002e8] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
 MEM: data read from cache_driver: ff00ff00
 PC: 800002ec ----> Received: ff00ff00 for addr: 80002004
-[800002e8] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
 
 ----
 READING - Addr: 80002004 = ff00ff00
@@ -40406,9 +40406,9 @@ PC: 800002ec ----> Received: babebabe for addr: 80002004
 ----
 READING - Addr: 80002004 = ff00ff00
 ******
+[800002e8] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
 MEM: data read from cache_driver: ff00ff00
 PC: 800002ec ----> Received: ff00ff00 for addr: 80002004
-[800002e8] WB Data: 00000000 {babebabe}, to register:  0 [1 0]
 
 ----
 READING - Addr: 80002004 = ff00ff00
@@ -40490,9 +40490,9 @@ PC: 80000310 ----> Received: babebabe for addr: 80002000
 ----
 READING - Addr: 80002000 = ff00ff
 ******
+[8000030c] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
 MEM: data read from cache_driver: 00ff00ff
 PC: 80000310 ----> Received: 00ff00ff for addr: 80002000
-[8000030c] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
 
 ----
 READING - Addr: 80002000 = ff00ff
@@ -40563,9 +40563,9 @@ PC: 8000032c ----> Received: babebabe for addr: 80002000
 ----
 READING - Addr: 80002000 = ff00ff
 ******
+[80000328] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
 MEM: data read from cache_driver: 00ff00ff
 PC: 8000032c ----> Received: 00ff00ff for addr: 80002000
-[80000328] WB Data: 80002000 {babebabe}, to register:  3 [1 0]
 
 ----
 READING - Addr: 80002000 = ff00ff
@@ -47055,8 +47055,8 @@ RF: Writing 80002002 to  1
 RF: Writing 80002204 to  4
 ----
 ******
-MEM: data read from cache_driver: ffffff98
 [80000208] WB Data: 80002009 {babebabe}, to register:  4 [1 0]
+MEM: data read from cache_driver: ffffff98
 
 ----
 ******
@@ -50716,8 +50716,8 @@ RF: Writing 8000200b to  1
 RF: Writing 80002230 to  4
 ----
 ******
-MEM: data read from cache_driver: 00003098
 [80000234] WB Data: 80002012 {babebabe}, to register:  4 [1 0]
+MEM: data read from cache_driver: 00003098
 
 ----
 ******
@@ -88272,9 +88272,9 @@ PC: 80000248 ----> Received: babebabe for addr: 80002024
 ----
 READING - Addr: 80002024 = 58213098
 ******
+[80000244] WB Data: 80002024 {babebabe}, to register:  4 [1 0]
 MEM: data read from cache_driver: 58213098
 PC: 80000248 ----> Received: 58213098 for addr: 80002024
-[80000244] WB Data: 80002024 {babebabe}, to register:  4 [1 0]
 
 ----
 READING - Addr: 80002024 = 58213098
diff --git a/rtl/obj_dir/test_bench.o b/rtl/obj_dir/test_bench.o
index 7d6d8cf9..a5d3fdc1 100644
Binary files a/rtl/obj_dir/test_bench.o and b/rtl/obj_dir/test_bench.o differ
diff --git a/rtl/results.txt b/rtl/results.txt
index 88562e2e..67713507 100644
--- a/rtl/results.txt
+++ b/rtl/results.txt
@@ -5,7 +5,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01843
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-addi.hex	****************
@@ -14,7 +14,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.03526
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-and.hex	****************
@@ -23,7 +23,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01849
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-andi.hex	****************
@@ -32,7 +32,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.04472
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-auipc.hex	****************
@@ -41,7 +41,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.16923
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-beq.hex	****************
@@ -50,7 +50,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.02552
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-bge.hex	****************
@@ -59,7 +59,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.02355
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-bgeu.hex	****************
@@ -68,7 +68,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.02236
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-blt.hex	****************
@@ -77,7 +77,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.02552
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-bltu.hex	****************
@@ -86,7 +86,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.02412
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-bne.hex	****************
@@ -95,7 +95,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.02552
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-jal.hex	****************
@@ -104,7 +104,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.18033
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-jalr.hex	****************
@@ -113,7 +113,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.07971
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-lb.hex	****************
@@ -122,7 +122,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.03323
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-lbu.hex	****************
@@ -131,7 +131,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.03323
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-lh.hex	****************
@@ -140,7 +140,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.03245
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-lhu.hex	****************
@@ -149,7 +149,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.03207
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-lui.hex	****************
@@ -158,7 +158,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.15068
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-lw.hex	****************
@@ -167,7 +167,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.03179
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-or.hex	****************
@@ -176,7 +176,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01839
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-ori.hex	****************
@@ -185,7 +185,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.04348
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-sb.hex	****************
@@ -194,7 +194,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01926
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-sh.hex	****************
@@ -203,7 +203,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01824
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-simple.hex	****************
@@ -212,7 +212,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.2973
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-sll.hex	****************
@@ -221,7 +221,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01738
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-slli.hex	****************
@@ -230,7 +230,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.03537
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-slt.hex	****************
@@ -239,7 +239,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01861
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-slti.hex	****************
@@ -248,7 +248,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.03583
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-sltiu.hex	****************
@@ -257,7 +257,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.03583
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-sltu.hex	****************
@@ -266,7 +266,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01861
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-sra.hex	****************
@@ -275,7 +275,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01682
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-srai.hex	****************
@@ -284,7 +284,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.03374
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-srl.hex	****************
@@ -293,7 +293,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01698
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-srli.hex	****************
@@ -302,7 +302,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.03438
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-sub.hex	****************
@@ -311,7 +311,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01874
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-sw.hex	****************
@@ -320,7 +320,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01797
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-xor.hex	****************
@@ -329,7 +329,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01843
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32ui-p-xori.hex	****************
@@ -338,7 +338,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.04314
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32um-p-div.hex	****************
@@ -347,7 +347,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.09821
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32um-p-divu.hex	****************
@@ -356,7 +356,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.09735
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32um-p-mul.hex	****************
@@ -365,7 +365,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.01868
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32um-p-mulh.hex	****************
@@ -374,7 +374,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.0188
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32um-p-mulhsu.hex	****************
@@ -383,7 +383,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.0188
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32um-p-mulhu.hex	****************
@@ -392,7 +392,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.0188
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32um-p-rem.hex	****************
@@ -401,7 +401,7 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.09821
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING
 
 ****************	../../emulator/riscv_tests/rv32um-p-remu.hex	****************
@@ -410,5 +410,5 @@
 # of forwarding stalls: 0
 # of branch stalls:     0
 # CPI:                  1.09821
-# time to simulate:     6.95313e-310 milliseconds
+# time to simulate:     6.95312e-310 milliseconds
 # GRADE:                PASSING