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Generated memory blocks for data cache (data), data cache (tag), shared memory

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This commit is contained in:
Lingjun Zhu
2019-10-20 14:52:28 -04:00
parent 797801ebae
commit 405926f66f
66 changed files with 706313 additions and 0 deletions
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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.bitmap Normal file
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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.cpf Normal file
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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.ctl Normal file
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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.mdt Normal file
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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.memlib Normal file
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/* logicvision_memcomp Version: c0.1.2-beta */
/* common_memcomp Version: c0.1.0-EAC */
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
//
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
//
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
//
// Use of this Software is subject to the terms and conditions of the
// applicable license agreement with ARM Physical IP, Inc.
// In addition, this Software is protected by patents, copyright law
// and international treaties.
//
// The copyright notice(s) in this Software does not indicate actual or
// intended publication of this Software.
//
// logicvision model for High Density Two Port Register File SVT MVT Compiler
//
// Instance Name: rf2_256x128_wm1
// Words: 256
// Bits: 128
// Mux: 2
// Drive: 6
// Write Mask: On
// Extra Margin Adjustment: On
// Redundant Rows: 0
// Redundant Columns: 2
// Test Muxes On
//
// Creation Date: Sun Oct 20 14:37:44 2019
// Version: r4p0
//
// Modeling Assumptions:
//
// Modeling Limitations: None
//
// Known Bugs: None.
//
// Known Work Arounds: N/A
//
MemoryTemplate (rf2_256x128_wm1) {
Algorithm : SmarchChkbvcd;
DataOutStage : None;
LogicalPorts : 1R1W;
BitGrouping : 1;
MemoryType : SRAM;
MinHold : 0.5;
OperationSet : SyncWRvcd;
SelectDuringWriteThru : Off;
ShadowRead : On;
ShadowWrite : On;
TransparentMode : None;
ObservationLogic: On;
InternalScanLogic: On;
CellName : rf2_256x128_wm1;
NumberOfWords : 256;
AddressCounter{
Function (Address) {
LogicalAddressMap{
ColumnAddress[0] : Address[0];
RowAddress[6:0] : Address[7:1];
}
}
Function (ColumnAddress) {
CountRange [0:1];
}
Function (RowAddress) {
CountRange [0:127];
}
}
PhysicalAddressMap{
ColumnAddress[0] : c[0];
RowAddress[0] : r[0];
RowAddress[1] : r[1];
RowAddress[2] : r[2];
RowAddress[3] : r[3];
RowAddress[4] : r[4];
RowAddress[5] : r[5];
RowAddress[6] : r[6];
}
PhysicalDataMap{
Data[0] : NOT d[0];
Data[1] : NOT d[1];
Data[2] : NOT d[2];
Data[3] : NOT d[3];
Data[4] : NOT d[4];
Data[5] : NOT d[5];
Data[6] : NOT d[6];
Data[7] : NOT d[7];
Data[8] : NOT d[8];
Data[9] : NOT d[9];
Data[10] : NOT d[10];
Data[11] : NOT d[11];
Data[12] : NOT d[12];
Data[13] : NOT d[13];
Data[14] : NOT d[14];
Data[15] : NOT d[15];
Data[16] : NOT d[16];
Data[17] : NOT d[17];
Data[18] : NOT d[18];
Data[19] : NOT d[19];
Data[20] : NOT d[20];
Data[21] : NOT d[21];
Data[22] : NOT d[22];
Data[23] : NOT d[23];
Data[24] : NOT d[24];
Data[25] : NOT d[25];
Data[26] : NOT d[26];
Data[27] : NOT d[27];
Data[28] : NOT d[28];
Data[29] : NOT d[29];
Data[30] : NOT d[30];
Data[31] : NOT d[31];
Data[32] : NOT d[32];
Data[33] : NOT d[33];
Data[34] : NOT d[34];
Data[35] : NOT d[35];
Data[36] : NOT d[36];
Data[37] : NOT d[37];
Data[38] : NOT d[38];
Data[39] : NOT d[39];
Data[40] : NOT d[40];
Data[41] : NOT d[41];
Data[42] : NOT d[42];
Data[43] : NOT d[43];
Data[44] : NOT d[44];
Data[45] : NOT d[45];
Data[46] : NOT d[46];
Data[47] : NOT d[47];
Data[48] : NOT d[48];
Data[49] : NOT d[49];
Data[50] : NOT d[50];
Data[51] : NOT d[51];
Data[52] : NOT d[52];
Data[53] : NOT d[53];
Data[54] : NOT d[54];
Data[55] : NOT d[55];
Data[56] : NOT d[56];
Data[57] : NOT d[57];
Data[58] : NOT d[58];
Data[59] : NOT d[59];
Data[60] : NOT d[60];
Data[61] : NOT d[61];
Data[62] : NOT d[62];
Data[63] : NOT d[63];
Data[64] : d[64];
Data[65] : d[65];
Data[66] : d[66];
Data[67] : d[67];
Data[68] : d[68];
Data[69] : d[69];
Data[70] : d[70];
Data[71] : d[71];
Data[72] : d[72];
Data[73] : d[73];
Data[74] : d[74];
Data[75] : d[75];
Data[76] : d[76];
Data[77] : d[77];
Data[78] : d[78];
Data[79] : d[79];
Data[80] : d[80];
Data[81] : d[81];
Data[82] : d[82];
Data[83] : d[83];
Data[84] : d[84];
Data[85] : d[85];
Data[86] : d[86];
Data[87] : d[87];
Data[88] : d[88];
Data[89] : d[89];
Data[90] : d[90];
Data[91] : d[91];
Data[92] : d[92];
Data[93] : d[93];
Data[94] : d[94];
Data[95] : d[95];
Data[96] : d[96];
Data[97] : d[97];
Data[98] : d[98];
Data[99] : d[99];
Data[100] : d[100];
Data[101] : d[101];
Data[102] : d[102];
Data[103] : d[103];
Data[104] : d[104];
Data[105] : d[105];
Data[106] : d[106];
Data[107] : d[107];
Data[108] : d[108];
Data[109] : d[109];
Data[110] : d[110];
Data[111] : d[111];
Data[112] : d[112];
Data[113] : d[113];
Data[114] : d[114];
Data[115] : d[115];
Data[116] : d[116];
Data[117] : d[117];
Data[118] : d[118];
Data[119] : d[119];
Data[120] : d[120];
Data[121] : d[121];
Data[122] : d[122];
Data[123] : d[123];
Data[124] : d[124];
Data[125] : d[125];
Data[126] : d[126];
Data[127] : d[127];
}
Port (AA[7:0]) {
Function : Address;
LogicalPort : A;
EmbeddedTestLogic {
TestInput : TAA[7:0];
TestOutput : AYA[7:0];
}
}
Port (QA[127:0]) {
Function : Data;
Direction : output;
LogicalPort : A;
}
Port (CENA) {
Function : ReadEnable;
LogicalPort : A;
Polarity : ActiveLow;
EmbeddedTestLogic {
TestInput : TCENA;
TestOutput : CENYA;
}
}
Port (TENA) {
Function : BISTOn;
Direction : Input;
LogicalPort : A;
Polarity : ActiveLow;
}
Port (CLKA) {
Function : Clock;
LogicalPort : A;
Polarity : ActiveHigh;
}
Port (EMAA[2:0]) {
Function : None;
SafeValue : 0;
Direction : Input;
LogicalPort : A;
Polarity : ActiveHigh;
}
Port (EMASA) {
Function : None;
SafeValue : 0;
Direction : Input;
LogicalPort : A;
Polarity : ActiveHigh;
}
port (SEA){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SIA[1:0]){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SOA[1:0]){
Function : None;
Direction : Output;
}
port (DFTRAMBYP){
Function : ScanTest;
Direction : Input;
Polarity : ActiveHigh;
}
Port (AB[7:0]) {
Function : Address;
LogicalPort : B;
EmbeddedTestLogic {
TestInput : TAB[7:0];
TestOutput : AYB[7:0];
}
}
Port (DB[127:0]) {
Function : Data;
Direction : input;
LogicalPort : B;
EmbeddedTestLogic {
TestInput : TDB[127:0];
}
}
Port (WENB[127:0]) {
Function : GroupWriteEnable;
BitsPerWriteEnable: 1;
LogicalPort : B;
Polarity : ActiveLow;
EmbeddedTestLogic {
TestInput : TWENB[127:0];
TestOutput : WENYB[127:0];
}
}
Port (CENB) {
Function : WriteEnable;
LogicalPort : B;
Polarity : ActiveLow;
EmbeddedTestLogic {
TestInput : TCENB;
TestOutput : CENYB;
}
}
Port (TENB) {
Function : BISTOn;
Direction : Input;
LogicalPort : B;
Polarity : ActiveLow;
}
Port (CLKB) {
Function : Clock;
LogicalPort : B;
Polarity : ActiveHigh;
}
Port (EMAB[2:0]) {
Function : None;
SafeValue : 0;
Direction : Input;
LogicalPort : B;
Polarity : ActiveHigh;
}
Port (COLLDISN) {
Function : None;
SafeValue : 1;
Direction : Input;
Polarity : ActiveLow;
}
port (SEB){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SIB[1:0]){
Function : None;
Direction : Input;
SafeValue : 0;
Polarity : ActiveHigh;
}
port (SOB[1:0]){
Function : None;
Direction : Output;
}
port (RET1N){
Function : None;
Direction : Input;
SafeValue : 1;
Polarity : Activelow;
}
}

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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_ff_0p99v_0p99v_125c.avm Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 20 14:34:36 2019
#
# Instance Options:
# Instance Name: rf2_256x128_wm1
# Number of Words: 256
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: avm
# AMCI Version: 1.4.3-EAC
# avm_memcomp Version: 2.1.1-EAC
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
rf2_256x128_wm1 {
MEMORY_TYPE RegFile
EQUIV_GATE_COUNT 36045
VDD_PIN VDDCE VDDPE
GND_PIN VSSE
#This file is for PROCESS FF, CORNER FF_0P99V_0P99V_125C
#However, RedHawk needs the process to be specified as 'PROCESS XX'
PROCESS XX
Cload 3.5e-05nF
VDD 0.99 0.99
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
Cpd avm_into_lowpwr {
VDDCE VSSE 1.60894e-04nF
VDDPE VSSE 6.29227e-04nF
}
PEAK_I avm_into_lowpwr {
VDDCE VSSE 4.02515mA
VDDPE VSSE 9.87592mA
}
Cpd avm_outof_lowpwr {
VDDCE VSSE 1.76983e-04nF
VDDPE VSSE 2.00800e-02nF
}
PEAK_I avm_outof_lowpwr {
VDDCE VSSE 4.42767mA
VDDPE VSSE 157.25220mA
}
Cpd avm_read_write {
VDDCE VSSE 3.67895e-04nF
VDDPE VSSE 1.19867e-02nF
}
PEAK_I avm_read_write {
VDDCE VSSE 10.77517mA
VDDPE VSSE 165.11481mA
}
Cpd avm_read_desel {
VDDCE VSSE 1.15700e-04nF
VDDPE VSSE 5.15571e-03nF
}
PEAK_I avm_read_desel {
VDDCE VSSE 3.18528mA
VDDPE VSSE 68.18280mA
}
Cpd avm_desel_write {
VDDCE VSSE 2.52195e-04nF
VDDPE VSSE 6.83102e-03nF
}
PEAK_I avm_desel_write {
VDDCE VSSE 8.13593mA
VDDPE VSSE 101.54025mA
}
Cpd avm_scan_capture {
VDDCE VSSE 8.09457e-06nF
VDDPE VSSE 1.07376e-02nF
}
PEAK_I avm_scan_capture {
VDDCE VSSE 0.43640mA
VDDPE VSSE 39.07064mA
}
Cpd avm_scan_shift {
VDDCE VSSE 8.09457e-06nF
VDDPE VSSE 1.07376e-02nF
}
PEAK_I avm_scan_shift {
VDDCE VSSE 0.43640mA
VDDPE VSSE 39.07064mA
}
Cpd standby_trig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.95501e-05nF
}
Cpd standby_ntrig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 2.17223e-05nF
}
LEAKAGE_I {
VDDCE VSSE 1.76745mA
VDDPE VSSE 2.45881mA
}
tsu 0.105188ns
ck2q_delay 0.580755ns
tr_q 0.013792ns
tf_q 0.015916ns
CHARACTERIZATION_MODE accurate
}

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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 20 14:35:01 2019
#
# Instance Options:
# Instance Name: rf2_256x128_wm1
# Number of Words: 256
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: datatable
# AMCI Version: 1.4.3-EAC
# datatable_memcomp Version: 1.3.0-amci
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
# Units used in Datatable :
# geomx: micron
# geomy: micron
# Voltage: volts
# Temprature: Degree Celsius
# Current: mA
# Time: ns
#
name ff_0p99v_0p99v_125c
S N
geomx 51.4050
geomy 414.8600
volt 0.9900
temp 125.0000
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
tcenacenya 0.0917
ttcenacenya 0.0905
ttenacenyapu 0.1191
ttenacenyanu 0.1400
tdftrambypcenya 0.1299
taaaya 0.0751
ttaaaya 0.0751
ttenaayapu 0.1377
ttenaayanu 0.1338
tdftrambypaya 0.1197
tcenbcenyb 0.0947
ttcenbcenyb 0.0939
ttenbcenybpu 0.1236
ttenbcenybnu 0.1996
tdftrambypcenyb 0.1226
twenbwenyb 0.0927
ttwenbwenyb 0.0930
ttenbwenybpu 0.2539
ttenbwenybnu 0.2667
tdftrambypwenyb 0.1651
tabayb 0.0753
ttabayb 0.0779
ttenbaybpu 0.1929
ttenbaybnu 0.1969
tdftrambypayb 0.1194
taccqa_rd0 0.5539
taccqa_rd1 0.5691
taccqa_rd2 0.5750
taccqa_rd3 0.5808
taccqa_rd4 0.6241
taccqa_rd5 0.6590
taccqa_rd6 0.7002
taccqa_rd7 0.7351
taccqa_scan0 0.5539
taccqa_scan1 0.5691
taccqa_scan2 0.5750
taccqa_scan3 0.5808
taccqa_scan4 0.6241
taccqa_scan5 0.6590
taccqa_scan6 0.7002
taccqa_scan7 0.7351
tclkasoa_rd0 0.5668
tclkasoa_rd1 0.5820
tclkasoa_rd2 0.5879
tclkasoa_rd3 0.5936
tclkasoa_rd4 0.6370
tclkasoa_rd5 0.6719
tclkasoa_rd6 0.7131
tclkasoa_rd7 0.7480
tclkasoa_scan0 0.5668
tclkasoa_scan1 0.5820
tclkasoa_scan2 0.5879
tclkasoa_scan3 0.5936
tclkasoa_scan4 0.6370
tclkasoa_scan5 0.6719
tclkasoa_scan6 0.7131
tclkasoa_scan7 0.7480
tclkbsob 0.2292
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
kload_cenya 1.7116
kload_aya 1.4236
kload_cenyb 1.6712
kload_wenyb 1.4498
kload_ayb 1.4006
kload_qa 0.5053
kload_soa 1.3720
kload_sob 1.4400
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
tcyca_ema0 0.7742
tcyca_ema1 0.7897
tcyca_ema2 0.7957
tcyca_ema3 0.8015
tcyca_ema4 0.8455
tcyca_ema5 0.8809
tcyca_ema6 0.9227
tcyca_ema7 0.9581
tcycb_ema0 0.9048
tcycb_ema1 0.9678
tcycb_ema2 0.9867
tcycb_ema3 1.0287
tcycb_ema4 1.0812
tcycb_ema5 1.1156
tcycb_ema6 1.1654
tcycb_ema7 1.2004
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
tcracwb_rd0 0.5748
tcracwb_rd1 0.5900
tcracwb_rd2 0.5959
tcracwb_rd3 0.6016
tcracwb_rd4 0.6450
tcracwb_rd5 0.6799
tcracwb_rd6 0.7211
tcracwb_rd7 0.7560
tcwbcra_wr0 0.6982
tcwbcra_wr1 0.7603
tcwbcra_wr2 0.7789
tcwbcra_wr3 0.8202
tcwbcra_wr4 0.8720
tcwbcra_wr5 0.9059
tcwbcra_wr6 0.9549
tcwbcra_wr7 0.9894
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
tckah 0.0927
tckal 0.0899
tckbh 0.0959
tckbl 0.0907
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
tcenas 0.1050
taas 0.1052
tcenbs 0.1076
twenbs 0.0150
tabs 0.1109
tdbs 0.0228
temaas 0.8268
temasas 0.8268
temabs 1.0540
ttenas 0.1862
ttcenas 0.1053
ttaas 0.1072
ttenbs 0.3890
ttcenbs 0.1081
ttwenbs 0.0151
ttabs 0.1146
ttdbs 0.0237
tsias 0.2048
tseas 0.2048
tdftrambypas 0.2426
tdftrambypbs 0.2426
tsibs 0.0228
tsebs 0.3890
tcolldisnas 0.8268
tcolldisnbs 1.0540
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
tcenah 0.0403
tcenaf_ret1nfh 1.0637
tcenaf_ret1nrh 0.4338
taah 0.0702
tcenbh 0.0423
tcenbf_ret1nfh 1.0637
tcenbf_ret1nrh 0.4338
twenbh 0.1736
tabh 0.0649
tdbh 0.1710
temaah 1.0484
temasah 1.0484
temabh 1.2354
ttenah 0.0772
ttcenah 0.0415
ttcenaf_ret1nfh 1.0637
ttcenaf_ret1nrh 0.4338
ttaah 0.0702
ttenbh 0.1918
ttcenbh 0.0436
ttcenbf_ret1nfh 1.0637
ttcenbf_ret1nrh 0.4338
ttwenbh 0.1743
ttabh 0.0649
ttdbh 0.1710
tret1nf_dftrambypfh 0.0270
tret1nr_dftrambypfh 1.0637
tret1nf_cenbrh 0.0270
tret1nf_cenarh 0.0263
tret1nf_tcenarh 0.0263
tret1nf_tcenbrh 0.0270
tret1nr_tcenbrh 1.0637
tret1nr_tcenarh 0.8365
tret1nr_cenbrh 1.0637
tret1nr_cenarh 0.8365
tsiah 0.0756
tseah 1.0484
tdftrambypah 1.0484
tdftrambypbh 1.0637
tdftrambypr_ret1nfh 1.0637
tdftrambypr_ret1nrh 0.4338
tsibh 0.1710
tsebh 0.1918
tcolldisnah 1.0484
tcolldisnbh 1.2354
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
icap_clka 0.0105
icap_cena 0.0018
icap_aa 0.0012
icap_clkb 0.0106
icap_cenb 0.0015
icap_wenb 0.0017
icap_ab 0.0012
icap_db 0.0019
icap_emaa 0.0059
icap_emasa 0.0021
icap_emab 0.0057
icap_tena 0.0010
icap_tcena 0.0016
icap_taa 0.0014
icap_tenb 0.0012
icap_tcenb 0.0016
icap_twenb 0.0015
icap_tab 0.0014
icap_tdb 0.0016
icap_sia 0.0015
icap_sea 0.0019
icap_dftrambyp 0.0021
icap_sib 0.0056
icap_seb 0.0019
icap_colldisn 0.0024
icap_ret1n 0.0035
# High Density Two Port Register File SVT MVT Compiler : current specific information.
icc_standby_c_chipdisable 1.767455
icc_standby_p_chipdisable 2.458812
icc_standby_c_ret1 2.056615
icc_standby_p_ret1 0.26801
icc_standby_c_selective_precharge 1.749951
icc_standby_p_selective_precharge 1.823619
icc_c_rd0_a 1.119e-04
icc_c_rd1_a 1.134e-04
icc_c_rd2_a 1.145e-04
icc_c_rd3_a 1.145e-04
icc_c_rd4_a 1.153e-04
icc_c_rd5_a 1.159e-04
icc_c_rd6_a 1.159e-04
icc_c_rd7_a 1.174e-04
icc_p_rd0_a 4.977e-03
icc_p_rd1_a 5.064e-03
icc_p_rd2_a 5.064e-03
icc_p_rd3_a 5.104e-03
icc_p_rd4_a 5.334e-03
icc_p_rd5_a 5.493e-03
icc_p_rd6_a 5.653e-03
icc_p_rd7_a 5.738e-03
icc_c_wr0_b 2.470e-04
icc_c_wr1_b 2.485e-04
icc_c_wr2_b 2.497e-04
icc_c_wr3_b 2.497e-04
icc_c_wr4_b 2.504e-04
icc_c_wr5_b 2.510e-04
icc_c_wr6_b 2.510e-04
icc_c_wr7_b 2.525e-04
icc_p_wr0_b 6.635e-03
icc_p_wr1_b 6.723e-03
icc_p_wr2_b 6.723e-03
icc_p_wr3_b 6.763e-03
icc_p_wr4_b 6.993e-03
icc_p_wr5_b 7.152e-03
icc_p_wr6_b 7.312e-03
icc_p_wr7_b 7.398e-03
icc_c_desela 0.000e+00
icc_p_desela 1.083e-04
icc_c_deselb 0.000e+00
icc_p_deselb 1.207e-03
icc_c_peak 10.775173
icc_p_peak 165.11481
icc_c_inrush 4.978407
icc_p_inrush 157.2522

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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_ff_0p99v_0p99v_125c.lib Normal file
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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_ff_0p99v_0p99v_125c.ps Normal file
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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_rtl.v Normal file
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/* verilog_rtl_memcomp Version: 4.0.5-beta11 */
/* common_memcomp Version: 4.0.5.2-amci */
/* lang compiler Version: 4.1.6-EAC2 Oct 30 2012 16:32:37 */
//
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
//
// Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
//
// Use of this Software is subject to the terms and conditions of the
// applicable license agreement with ARM Physical IP, Inc.
// In addition, this Software is protected by patents, copyright law
// and international treaties.
//
// The copyright notice(s) in this Software does not indicate actual or
// intended publication of this Software.
//
// Repair Verilog RTL for High Density Two Port Register File SVT MVT Compiler
//
// Instance Name: rf2_256x128_wm1_rtl_top
// Words: 256
// User Bits: 128
// Mux: 2
// Drive: 6
// Write Mask: On
// Extra Margin Adjustment: On
// Redundancy: off
// Redundant Rows: 0
// Redundant Columns: 2
// Test Muxes On
// Ser: none
// Retention: on
// Power Gating: off
//
// Creation Date: Sun Oct 20 14:38:18 2019
// Version: r4p0
//
// Verified
//
// Known Bugs: None.
//
// Known Work Arounds: N/A
//
`timescale 1ns/1ps
module rf2_256x128_wm1_rtl_top (
CENYA,
AYA,
CENYB,
WENYB,
AYB,
QA,
SOA,
SOB,
CLKA,
CENA,
AA,
CLKB,
CENB,
WENB,
AB,
DB,
EMAA,
EMASA,
EMAB,
TENA,
TCENA,
TAA,
TENB,
TCENB,
TWENB,
TAB,
TDB,
RET1N,
SIA,
SEA,
DFTRAMBYP,
SIB,
SEB,
COLLDISN
);
output CENYA;
output [7:0] AYA;
output CENYB;
output [127:0] WENYB;
output [7:0] AYB;
output [127:0] QA;
output [1:0] SOA;
output [1:0] SOB;
input CLKA;
input CENA;
input [7:0] AA;
input CLKB;
input CENB;
input [127:0] WENB;
input [7:0] AB;
input [127:0] DB;
input [2:0] EMAA;
input EMASA;
input [2:0] EMAB;
input TENA;
input TCENA;
input [7:0] TAA;
input TENB;
input TCENB;
input [127:0] TWENB;
input [7:0] TAB;
input [127:0] TDB;
input RET1N;
input [1:0] SIA;
input SEA;
input DFTRAMBYP;
input [1:0] SIB;
input SEB;
input COLLDISN;
wire [127:0] QOA;
wire [127:0] DIB;
assign QA = QOA;
assign DIB = DB;
rf2_256x128_wm1_fr_top u0 (
.CENYA(CENYA),
.AYA(AYA),
.CENYB(CENYB),
.WENYB(WENYB),
.AYB(AYB),
.QOA(QOA),
.SOA(SOA),
.SOB(SOB),
.CLKA(CLKA),
.CENA(CENA),
.AA(AA),
.CLKB(CLKB),
.CENB(CENB),
.WENB(WENB),
.AB(AB),
.DIB(DIB),
.EMAA(EMAA),
.EMASA(EMASA),
.EMAB(EMAB),
.TENA(TENA),
.TCENA(TCENA),
.TAA(TAA),
.TENB(TENB),
.TCENB(TCENB),
.TWENB(TWENB),
.TAB(TAB),
.TDB(TDB),
.RET1N(RET1N),
.SIA(SIA),
.SEA(SEA),
.DFTRAMBYP(DFTRAMBYP),
.SIB(SIB),
.SEB(SEB),
.COLLDISN(COLLDISN)
);
endmodule
module rf2_256x128_wm1_fr_top (
CENYA,
AYA,
CENYB,
WENYB,
AYB,
QOA,
SOA,
SOB,
CLKA,
CENA,
AA,
CLKB,
CENB,
WENB,
AB,
DIB,
EMAA,
EMASA,
EMAB,
TENA,
TCENA,
TAA,
TENB,
TCENB,
TWENB,
TAB,
TDB,
RET1N,
SIA,
SEA,
DFTRAMBYP,
SIB,
SEB,
COLLDISN
);
output CENYA;
output [7:0] AYA;
output CENYB;
output [127:0] WENYB;
output [7:0] AYB;
output [127:0] QOA;
output [1:0] SOA;
output [1:0] SOB;
input CLKA;
input CENA;
input [7:0] AA;
input CLKB;
input CENB;
input [127:0] WENB;
input [7:0] AB;
input [127:0] DIB;
input [2:0] EMAA;
input EMASA;
input [2:0] EMAB;
input TENA;
input TCENA;
input [7:0] TAA;
input TENB;
input TCENB;
input [127:0] TWENB;
input [7:0] TAB;
input [127:0] TDB;
input RET1N;
input [1:0] SIA;
input SEA;
input DFTRAMBYP;
input [1:0] SIB;
input SEB;
input COLLDISN;
wire [127:0] DB;
wire [127:0] QA;
assign DB=DIB;
assign QOA=QA;
rf2_256x128_wm1 u0 (
.CENYA(CENYA),
.AYA(AYA),
.CENYB(CENYB),
.WENYB(WENYB),
.AYB(AYB),
.QA(QA),
.SOA(SOA),
.SOB(SOB),
.CLKA(CLKA),
.CENA(CENA),
.AA(AA),
.CLKB(CLKB),
.CENB(CENB),
.WENB(WENB),
.AB(AB),
.DB(DB),
.EMAA(EMAA),
.EMASA(EMASA),
.EMAB(EMAB),
.TENA(TENA),
.TCENA(TCENA),
.TAA(TAA),
.TENB(TENB),
.TCENB(TCENB),
.TWENB(TWENB),
.TAB(TAB),
.TDB(TDB),
.RET1N(RET1N),
.SIA(SIA),
.SEA(SEA),
.DFTRAMBYP(DFTRAMBYP),
.SIB(SIB),
.SEB(SEB),
.COLLDISN(COLLDISN)
);
endmodule // rf2_256x128_wm1_fr_top

162
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.avm Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 20 14:34:42 2019
#
# Instance Options:
# Instance Name: rf2_256x128_wm1
# Number of Words: 256
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: avm
# AMCI Version: 1.4.3-EAC
# avm_memcomp Version: 2.1.1-EAC
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
rf2_256x128_wm1 {
MEMORY_TYPE RegFile
EQUIV_GATE_COUNT 36045
VDD_PIN VDDCE VDDPE
GND_PIN VSSE
#This file is for PROCESS SS, CORNER SS_0P81V_0P81V_M40C
#However, RedHawk needs the process to be specified as 'PROCESS XX'
PROCESS XX
Cload 3.5e-05nF
VDD 0.81 0.81
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
Cpd avm_into_lowpwr {
VDDCE VSSE 1.36450e-04nF
VDDPE VSSE 5.69028e-04nF
}
PEAK_I avm_into_lowpwr {
VDDCE VSSE 1.38817mA
VDDPE VSSE 3.40465mA
}
Cpd avm_outof_lowpwr {
VDDCE VSSE 1.50095e-04nF
VDDPE VSSE 1.99757e-02nF
}
PEAK_I avm_outof_lowpwr {
VDDCE VSSE 1.52699mA
VDDPE VSSE 54.53884mA
}
Cpd avm_read_write {
VDDCE VSSE 3.02086e-04nF
VDDPE VSSE 1.12684e-02nF
}
PEAK_I avm_read_write {
VDDCE VSSE 3.03008mA
VDDPE VSSE 57.13365mA
}
Cpd avm_read_desel {
VDDCE VSSE 1.11001e-04nF
VDDPE VSSE 4.76672e-03nF
}
PEAK_I avm_read_desel {
VDDCE VSSE 0.98347mA
VDDPE VSSE 24.69243mA
}
Cpd avm_desel_write {
VDDCE VSSE 1.91085e-04nF
VDDPE VSSE 6.50167e-03nF
}
PEAK_I avm_desel_write {
VDDCE VSSE 2.00722mA
VDDPE VSSE 32.81133mA
}
Cpd avm_scan_capture {
VDDCE VSSE 8.14454e-06nF
VDDPE VSSE 9.88468e-03nF
}
PEAK_I avm_scan_capture {
VDDCE VSSE 0.14129mA
VDDPE VSSE 13.03296mA
}
Cpd avm_scan_shift {
VDDCE VSSE 8.14454e-06nF
VDDPE VSSE 9.88468e-03nF
}
PEAK_I avm_scan_shift {
VDDCE VSSE 0.14129mA
VDDPE VSSE 13.03296mA
}
Cpd standby_trig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.69190e-05nF
}
Cpd standby_ntrig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.87989e-05nF
}
LEAKAGE_I {
VDDCE VSSE 1.48000e-03mA
VDDPE VSSE 1.00800e-03mA
}
tsu 0.30673ns
ck2q_delay 1.23487ns
tr_q 0.034858ns
tf_q 0.039745ns
CHARACTERIZATION_MODE accurate
}

334
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.dat Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 20 14:35:06 2019
#
# Instance Options:
# Instance Name: rf2_256x128_wm1
# Number of Words: 256
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: datatable
# AMCI Version: 1.4.3-EAC
# datatable_memcomp Version: 1.3.0-amci
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
# Units used in Datatable :
# geomx: micron
# geomy: micron
# Voltage: volts
# Temprature: Degree Celsius
# Current: mA
# Time: ns
#
name ss_0p81v_0p81v_m40c
S N
geomx 51.4050
geomy 414.8600
volt 0.8100
temp -40.0000
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
tcenacenya 0.2145
ttcenacenya 0.2108
ttenacenyapu 0.3026
ttenacenyanu 0.3541
tdftrambypcenya 0.3853
taaaya 0.2110
ttaaaya 0.2184
ttenaayapu 0.3904
ttenaayanu 0.3751
tdftrambypaya 0.3736
tcenbcenyb 0.2113
ttcenbcenyb 0.2108
ttenbcenybpu 0.3045
ttenbcenybnu 0.5445
tdftrambypcenyb 0.3738
twenbwenyb 0.2952
ttwenbwenyb 0.2956
ttenbwenybpu 0.6920
ttenbwenybnu 0.7096
tdftrambypwenyb 0.4014
tabayb 0.2105
ttabayb 0.2161
ttenbaybpu 0.5881
ttenbaybnu 0.5463
tdftrambypayb 0.3669
taccqa_rd0 1.1578
taccqa_rd1 1.2052
taccqa_rd2 1.2130
taccqa_rd3 1.2349
taccqa_rd4 1.3452
taccqa_rd5 1.4641
taccqa_rd6 1.5960
taccqa_rd7 1.7145
taccqa_scan0 1.1578
taccqa_scan1 1.2052
taccqa_scan2 1.2130
taccqa_scan3 1.2349
taccqa_scan4 1.3452
taccqa_scan5 1.4641
taccqa_scan6 1.5960
taccqa_scan7 1.7145
tclkasoa_rd0 1.2615
tclkasoa_rd1 1.3089
tclkasoa_rd2 1.3167
tclkasoa_rd3 1.3386
tclkasoa_rd4 1.4489
tclkasoa_rd5 1.5678
tclkasoa_rd6 1.6997
tclkasoa_rd7 1.8182
tclkasoa_scan0 1.2615
tclkasoa_scan1 1.3089
tclkasoa_scan2 1.3167
tclkasoa_scan3 1.3386
tclkasoa_scan4 1.4489
tclkasoa_scan5 1.5678
tclkasoa_scan6 1.6997
tclkasoa_scan7 1.8182
tclkbsob 0.5287
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
kload_cenya 3.3060
kload_aya 2.7500
kload_cenyb 3.3440
kload_wenyb 3.0700
kload_ayb 2.7720
kload_qa 1.0935
kload_soa 2.7600
kload_sob 3.1660
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
tcyca_ema0 1.6962
tcyca_ema1 1.7444
tcyca_ema2 1.7524
tcyca_ema3 1.7745
tcyca_ema4 1.8864
tcyca_ema5 2.0071
tcyca_ema6 2.1411
tcyca_ema7 2.2613
tcycb_ema0 1.9005
tcycb_ema1 2.0932
tcycb_ema2 2.1705
tcycb_ema3 2.3041
tcycb_ema4 2.4369
tcycb_ema5 2.5494
tcycb_ema6 2.7016
tcycb_ema7 2.8221
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
tcracwb_rd0 0.9660
tcracwb_rd1 1.0134
tcracwb_rd2 1.0212
tcracwb_rd3 1.0431
tcracwb_rd4 1.1534
tcracwb_rd5 1.2723
tcracwb_rd6 1.4042
tcracwb_rd7 1.5227
tcwbcra_wr0 1.3612
tcwbcra_wr1 1.5512
tcwbcra_wr2 1.6273
tcwbcra_wr3 1.7590
tcwbcra_wr4 1.8898
tcwbcra_wr5 2.0006
tcwbcra_wr6 2.1506
tcwbcra_wr7 2.2692
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
tckah 0.1789
tckal 0.1936
tckbh 0.1811
tckbl 0.1760
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
tcenas 0.2616
taas 0.3067
tcenbs 0.2580
twenbs 0.0857
tabs 0.3108
tdbs 0.1681
temaas 1.8578
temasas 1.8578
temabs 2.3875
ttenas 0.4973
ttcenas 0.2628
ttaas 0.3154
ttenbs 0.8279
ttcenbs 0.2586
ttwenbs 0.0862
ttabs 0.3179
ttdbs 0.1738
tsias 0.5470
tseas 0.5470
tdftrambypas 0.7164
tdftrambypbs 0.7164
tsibs 0.1681
tsebs 0.8279
tcolldisnas 1.8578
tcolldisnbs 2.3875
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
tcenah 0.0852
tcenaf_ret1nfh 2.3683
tcenaf_ret1nrh 0.9924
taah 0.1420
tcenbh 0.0853
tcenbf_ret1nfh 2.3683
tcenbf_ret1nrh 0.9924
twenbh 0.3114
tabh 0.1299
tdbh 0.3013
temaah 2.5228
temasah 2.5228
temabh 2.8863
ttenah 0.1562
ttcenah 0.0868
ttcenaf_ret1nfh 2.3683
ttcenaf_ret1nrh 0.9924
ttaah 0.1420
ttenbh 0.3425
ttcenbh 0.0866
ttcenbf_ret1nfh 2.3683
ttcenbf_ret1nrh 0.9924
ttwenbh 0.3114
ttabh 0.1299
ttdbh 0.3013
tret1nf_dftrambypfh 0.0657
tret1nr_dftrambypfh 2.3683
tret1nf_cenbrh 0.0646
tret1nf_cenarh 0.0657
tret1nf_tcenarh 0.0657
tret1nf_tcenbrh 0.0646
tret1nr_tcenbrh 2.3683
tret1nr_tcenarh 1.8386
tret1nr_cenbrh 2.3683
tret1nr_cenarh 1.8386
tsiah 0.1246
tseah 2.5228
tdftrambypah 2.5228
tdftrambypbh 2.3683
tdftrambypr_ret1nfh 2.3683
tdftrambypr_ret1nrh 0.9924
tsibh 0.3013
tsebh 0.3425
tcolldisnah 2.5228
tcolldisnbh 2.8863
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
icap_clka 0.0087
icap_cena 0.0014
icap_aa 0.0017
icap_clkb 0.0088
icap_cenb 0.0011
icap_wenb 0.0016
icap_ab 0.0015
icap_db 0.0018
icap_emaa 0.0056
icap_emasa 0.0021
icap_emab 0.0054
icap_tena 0.0008
icap_tcena 0.0012
icap_taa 0.0016
icap_tenb 0.0009
icap_tcenb 0.0012
icap_twenb 0.0014
icap_tab 0.0014
icap_tdb 0.0015
icap_sia 0.0011
icap_sea 0.0016
icap_dftrambyp 0.0016
icap_sib 0.0054
icap_seb 0.0017
icap_colldisn 0.0021
icap_ret1n 0.0032
# High Density Two Port Register File SVT MVT Compiler : current specific information.
icc_standby_c_chipdisable 1.480e-03
icc_standby_p_chipdisable 1.008e-03
icc_standby_c_ret1 1.476e-03
icc_standby_p_ret1 7.112e-06
icc_standby_c_selective_precharge 1.473e-03
icc_standby_p_selective_precharge 3.757e-04
icc_c_rd0_a 8.975e-05
icc_c_rd1_a 8.975e-05
icc_c_rd2_a 8.991e-05
icc_c_rd3_a 8.991e-05
icc_c_rd4_a 9.031e-05
icc_c_rd5_a 9.135e-05
icc_c_rd6_a 9.197e-05
icc_c_rd7_a 9.199e-05
icc_p_rd0_a 3.725e-03
icc_p_rd1_a 3.805e-03
icc_p_rd2_a 3.839e-03
icc_p_rd3_a 3.861e-03
icc_p_rd4_a 4.110e-03
icc_p_rd5_a 4.285e-03
icc_p_rd6_a 4.387e-03
icc_p_rd7_a 4.441e-03
icc_c_wr0_b 1.546e-04
icc_c_wr1_b 1.546e-04
icc_c_wr2_b 1.548e-04
icc_c_wr3_b 1.548e-04
icc_c_wr4_b 1.552e-04
icc_c_wr5_b 1.562e-04
icc_c_wr6_b 1.568e-04
icc_c_wr7_b 1.569e-04
icc_p_wr0_b 5.130e-03
icc_p_wr1_b 5.210e-03
icc_p_wr2_b 5.245e-03
icc_p_wr3_b 5.266e-03
icc_p_wr4_b 5.515e-03
icc_p_wr5_b 5.690e-03
icc_p_wr6_b 5.792e-03
icc_p_wr7_b 5.846e-03
icc_c_desela 0.000e+00
icc_p_desela 7.685e-05
icc_c_deselb 0.000e+00
icc_p_deselb 9.096e-04
icc_c_peak 3.03008
icc_p_peak 57.133648
icc_c_inrush 1.397455
icc_p_inrush 54.412998

72824
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.lib Normal file
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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_ss_0p81v_0p81v_m40c.ps Normal file
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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_tt_0p90v_0p90v_25c.avm Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 20 14:34:49 2019
#
# Instance Options:
# Instance Name: rf2_256x128_wm1
# Number of Words: 256
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: avm
# AMCI Version: 1.4.3-EAC
# avm_memcomp Version: 2.1.1-EAC
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
rf2_256x128_wm1 {
MEMORY_TYPE RegFile
EQUIV_GATE_COUNT 36045
VDD_PIN VDDCE VDDPE
GND_PIN VSSE
#This file is for PROCESS TT, CORNER TT_0P90V_0P90V_25C
#However, RedHawk needs the process to be specified as 'PROCESS XX'
PROCESS XX
Cload 3.5e-05nF
VDD 0.9 0.9
state_boolean avm_into_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!RET1N&!DFTRAMBYP)" "!RET1N" "NA"
state_boolean avm_outof_lowpwr "(((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&RET1N&!DFTRAMBYP)" "RET1N" "NA"
state_boolean avm_read_write "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_read_desel "RET1N&!DFTRAMBYP&((CLKA&TENA&!CENA)|(CLKA&!TENA&!TCENA))&((CLKB&TENB&CENB)|(CLKB&!TENB&TCENB))" "CLKA CLKB" "NA"
state_boolean avm_desel_write "RET1N&!DFTRAMBYP&((CLKA&TENA&CENA)|(CLKA&!TENA&TCENA))&((CLKB&TENB&!CENB)|(CLKB&!TENB&!TCENB))" "CLKA CLKB" "NA"
state_boolean avm_scan_capture "((CLKA&!SEA&RET1N&DFTRAMBYP)&(CLKB&!SEB&RET1N&DFTRAMBYP))" "DFTRAMBYP" "NA"
state_boolean avm_scan_shift "(CLKA&SEA&RET1N&DFTRAMBYP)&(CLKB&SEB&RET1N&DFTRAMBYP)" "DFTRAMBYP" "NA"
state_boolean standby_trig "RET1N&((CLKA&CENA&TENA)|(CLKA&TCENA&!TENA))&((CLKB&CENB&TENB)|(CLKB&TCENB&!TENB))&!DFTRAMBYP" "CLKA CLKB" "NA"
state_boolean standby_ntrig "RET1N&((!CLKA&CENA&TENA)|(!CLKA&TCENA&!TENA))&((!CLKB&CENB&TENB)|(!CLKB&TCENB&!TENB))&!DFTRAMBYP" "!CLKA !CLKB" "NA"
Cpd avm_into_lowpwr {
VDDCE VSSE 1.46123e-04nF
VDDPE VSSE 5.81140e-04nF
}
PEAK_I avm_into_lowpwr {
VDDCE VSSE 2.51801mA
VDDPE VSSE 5.85375mA
}
Cpd avm_outof_lowpwr {
VDDCE VSSE 1.60735e-04nF
VDDPE VSSE 2.06310e-02nF
}
PEAK_I avm_outof_lowpwr {
VDDCE VSSE 2.76981mA
VDDPE VSSE 97.44930mA
}
Cpd avm_read_write {
VDDCE VSSE 3.28585e-04nF
VDDPE VSSE 1.15071e-02nF
}
PEAK_I avm_read_write {
VDDCE VSSE 6.02046mA
VDDPE VSSE 102.32177mA
}
Cpd avm_read_desel {
VDDCE VSSE 1.13920e-04nF
VDDPE VSSE 4.91994e-03nF
}
PEAK_I avm_read_desel {
VDDCE VSSE 1.74222mA
VDDPE VSSE 43.45212mA
}
Cpd avm_desel_write {
VDDCE VSSE 2.14665e-04nF
VDDPE VSSE 6.58721e-03nF
}
PEAK_I avm_desel_write {
VDDCE VSSE 4.09592mA
VDDPE VSSE 61.21476mA
}
Cpd avm_scan_capture {
VDDCE VSSE 8.56193e-06nF
VDDPE VSSE 1.02363e-02nF
}
PEAK_I avm_scan_capture {
VDDCE VSSE 0.27530mA
VDDPE VSSE 24.42748mA
}
Cpd avm_scan_shift {
VDDCE VSSE 8.56193e-06nF
VDDPE VSSE 1.02363e-02nF
}
PEAK_I avm_scan_shift {
VDDCE VSSE 0.27530mA
VDDPE VSSE 24.42748mA
}
Cpd standby_trig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.77000e-05nF
}
Cpd standby_ntrig {
VDDCE VSSE 0.00000e+00nF
VDDPE VSSE 1.96666e-05nF
}
LEAKAGE_I {
VDDCE VSSE 1.27820e-02mA
VDDPE VSSE 1.52060e-02mA
}
tsu 0.146718ns
ck2q_delay 0.73198ns
tr_q 0.018874ns
tf_q 0.022096ns
CHARACTERIZATION_MODE accurate
}

334
models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_tt_0p90v_0p90v_25c.dat Normal file
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#
# CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM PHYSICAL IP, INC.
#
# Copyright (c) 1993 - 2019 ARM Physical IP, Inc. All Rights Reserved.
#
# Use of this Software is subject to the terms and conditions of the
# applicable license agreement with ARM Physical IP, Inc.
# In addition, this Software is protected by patents, copyright law
# and international treaties.
#
# The copyright notice(s) in this Software does not indicate actual or
# intended publication of this Software.
#
# Compiler Name: High Density Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 20 14:35:10 2019
#
# Instance Options:
# Instance Name: rf2_256x128_wm1
# Number of Words: 256
# Number of Bits: 128
# Multiplexer Width: 2
# Multi-Vt selection: BASE
# Frequency <MHz>: 1
# Activity Factor <%>: 50
# Pipeline: off
# Word-Write Mask: on
# Word Partition Size: 1
# Write through: off
# Top Metal Layer: m5-m10
# Power Type: otc
# Redundancy: off
# Redundant Columns: 2
# Redundant Rows: 0
# BIST MUXes: on
# Soft Error Repair (SER): none
# Power Gating: off
# Back Biasing: off
# Retention: on
# Extra Margin Adjustment: on
# Advanced Test Features: off
# Customer Comment: This is a memory instance
# Bus-notation: on
# Power Ground Rename: vddpe:VDDPE,vddce:VDDCE,vsse:VSSE
# Name Case: upper
# Check Instance Name: off
# Diodes: on
# Drive Strength: 6
# Site Definitions: off
# Library Name: USERLIB
# Liberty setting: nldm
#
# Compiler Versions:
# Memory Version: r4p0
# Lang compiler Version: 4.1.6-EAC2
# View Name: datatable
# AMCI Version: 1.4.3-EAC
# datatable_memcomp Version: 1.3.0-amci
#
# Modeling Assumptions: N/A
#
# Modeling Limitations: N/A
#
# Known Bugs: N/A
#
# Known Work Arounds: N/A
#
# Units used in Datatable :
# geomx: micron
# geomy: micron
# Voltage: volts
# Temprature: Degree Celsius
# Current: mA
# Time: ns
#
name tt_0p90v_0p90v_25c
S N
geomx 51.4050
geomy 414.8600
volt 0.9000
temp 25.0000
# High Density Two Port Register File SVT MVT Compiler : Propagation Delay specific information.
tcenacenya 0.1187
ttcenacenya 0.1176
ttenacenyapu 0.1613
ttenacenyanu 0.1885
tdftrambypcenya 0.1900
taaaya 0.1038
ttaaaya 0.1082
ttenaayapu 0.1877
ttenaayanu 0.1835
tdftrambypaya 0.1776
tcenbcenyb 0.1195
ttcenbcenyb 0.1185
ttenbcenybpu 0.1658
ttenbcenybnu 0.2823
tdftrambypcenyb 0.1824
twenbwenyb 0.1351
ttwenbwenyb 0.1341
ttenbwenybpu 0.3463
ttenbwenybnu 0.3615
tdftrambypwenyb 0.2183
tabayb 0.1040
ttabayb 0.1062
ttenbaybpu 0.2796
ttenbaybnu 0.2792
tdftrambypayb 0.1779
taccqa_rd0 0.6912
taccqa_rd1 0.7160
taccqa_rd2 0.7230
taccqa_rd3 0.7320
taccqa_rd4 0.7886
taccqa_rd5 0.8424
taccqa_rd6 0.8983
taccqa_rd7 0.9521
taccqa_scan0 0.6912
taccqa_scan1 0.7160
taccqa_scan2 0.7230
taccqa_scan3 0.7320
taccqa_scan4 0.7886
taccqa_scan5 0.8424
taccqa_scan6 0.8983
taccqa_scan7 0.9521
tclkasoa_rd0 0.7252
tclkasoa_rd1 0.7501
tclkasoa_rd2 0.7570
tclkasoa_rd3 0.7660
tclkasoa_rd4 0.8227
tclkasoa_rd5 0.8764
tclkasoa_rd6 0.9324
tclkasoa_rd7 0.9862
tclkasoa_scan0 0.7252
tclkasoa_scan1 0.7501
tclkasoa_scan2 0.7570
tclkasoa_scan3 0.7660
tclkasoa_scan4 0.8227
tclkasoa_scan5 0.8764
tclkasoa_scan6 0.9324
tclkasoa_scan7 0.9862
tclkbsob 0.2966
# High Density Two Port Register File SVT MVT Compiler : Kload specific information.
kload_cenya 2.0800
kload_aya 1.6620
kload_cenyb 1.9640
kload_wenyb 1.7940
kload_ayb 1.6740
kload_qa 0.6365
kload_soa 1.7020
kload_sob 1.8420
# High Density Two Port Register File SVT MVT Compiler : Cycle time specific information.
tcyca_ema0 0.9855
tcyca_ema1 1.0107
tcyca_ema2 1.0178
tcyca_ema3 1.0269
tcyca_ema4 1.0845
tcyca_ema5 1.1390
tcyca_ema6 1.1958
tcyca_ema7 1.2504
tcycb_ema0 1.0536
tcycb_ema1 1.1407
tcycb_ema2 1.1704
tcycb_ema3 1.2298
tcycb_ema4 1.2998
tcycb_ema5 1.3506
tcycb_ema6 1.4216
tcycb_ema7 1.4725
# High Density Two Port Register File SVT MVT Compiler : Clock collision specific information.
tcracwb_rd0 0.6691
tcracwb_rd1 0.6939
tcracwb_rd2 0.7009
tcracwb_rd3 0.7099
tcracwb_rd4 0.7665
tcracwb_rd5 0.8203
tcracwb_rd6 0.8762
tcracwb_rd7 0.9300
tcwbcra_wr0 0.8352
tcwbcra_wr1 0.9210
tcwbcra_wr2 0.9503
tcwbcra_wr3 1.0088
tcwbcra_wr4 1.0777
tcwbcra_wr5 1.1277
tcwbcra_wr6 1.1978
tcwbcra_wr7 1.2478
# High Density Two Port Register File SVT MVT Compiler : Pulse width specific information.
tckah 0.1135
tckal 0.1131
tckbh 0.1160
tckbl 0.1128
# High Density Two Port Register File SVT MVT Compiler : Setup time specific information.
tcenas 0.1417
taas 0.1467
tcenbs 0.1422
twenbs 0.0225
tabs 0.1545
tdbs 0.0487
temaas 1.0667
temasas 1.0667
temabs 1.2696
ttenas 0.2541
ttcenas 0.1417
ttaas 0.1512
ttenbs 0.4755
ttcenbs 0.1434
ttwenbs 0.0225
ttabs 0.1580
ttdbs 0.0509
tsias 0.2795
tseas 0.2795
tdftrambypas 0.3488
tdftrambypbs 0.3488
tsibs 0.0487
tsebs 0.4755
tcolldisnas 1.0667
tcolldisnbs 1.2696
# High Density Two Port Register File SVT MVT Compiler : Hold time specific information.
tcenah 0.0495
tcenaf_ret1nfh 1.2730
tcenaf_ret1nrh 0.5521
taah 0.0840
tcenbh 0.0496
tcenbf_ret1nfh 1.2730
tcenbf_ret1nrh 0.5521
twenbh 0.2057
tabh 0.0788
tdbh 0.1941
temaah 1.3783
temasah 1.3783
temabh 1.5157
ttenah 0.0924
ttcenah 0.0524
ttcenaf_ret1nfh 1.2730
ttcenaf_ret1nrh 0.5521
ttaah 0.0840
ttenbh 0.2271
ttcenbh 0.0510
ttcenbf_ret1nfh 1.2730
ttcenbf_ret1nrh 0.5521
ttwenbh 0.2065
ttabh 0.0788
ttdbh 0.1941
tret1nf_dftrambypfh 0.0358
tret1nr_dftrambypfh 1.2730
tret1nf_cenbrh 0.0358
tret1nf_cenarh 0.0354
tret1nf_tcenarh 0.0354
tret1nf_tcenbrh 0.0358
tret1nr_tcenbrh 1.2730
tret1nr_tcenarh 1.0701
tret1nr_cenbrh 1.2730
tret1nr_cenarh 1.0701
tsiah 0.0817
tseah 1.3783
tdftrambypah 1.3783
tdftrambypbh 1.2730
tdftrambypr_ret1nfh 1.2730
tdftrambypr_ret1nrh 0.5521
tsibh 0.1941
tsebh 0.2271
tcolldisnah 1.3783
tcolldisnbh 1.5157
# High Density Two Port Register File SVT MVT Compiler : Input Capacitance specific information.
icap_clka 0.0091
icap_cena 0.0013
icap_aa 0.0016
icap_clkb 0.0097
icap_cenb 0.0013
icap_wenb 0.0014
icap_ab 0.0016
icap_db 0.0019
icap_emaa 0.0058
icap_emasa 0.0025
icap_emab 0.0056
icap_tena 0.0009
icap_tcena 0.0014
icap_taa 0.0015
icap_tenb 0.0010
icap_tcenb 0.0014
icap_twenb 0.0012
icap_tab 0.0016
icap_tdb 0.0016
icap_sia 0.0012
icap_sea 0.0016
icap_dftrambyp 0.0021
icap_sib 0.0058
icap_seb 0.0019
icap_colldisn 0.0021
icap_ret1n 0.0034
# High Density Two Port Register File SVT MVT Compiler : current specific information.
icc_standby_c_chipdisable 0.012782
icc_standby_p_chipdisable 0.015206
icc_standby_c_ret1 0.013463
icc_standby_p_ret1 1.006e-03
icc_standby_c_selective_precharge 0.012632
icc_standby_p_selective_precharge 0.01099
icc_c_rd0_a 1.021e-04
icc_c_rd1_a 1.025e-04
icc_c_rd2_a 1.025e-04
icc_c_rd3_a 1.025e-04
icc_c_rd4_a 1.052e-04
icc_c_rd5_a 1.057e-04
icc_c_rd6_a 1.057e-04
icc_c_rd7_a 1.073e-04
icc_p_rd0_a 4.288e-03
icc_p_rd1_a 4.372e-03
icc_p_rd2_a 4.389e-03
icc_p_rd3_a 4.428e-03
icc_p_rd4_a 4.684e-03
icc_p_rd5_a 4.855e-03
icc_p_rd6_a 5.030e-03
icc_p_rd7_a 5.100e-03
icc_c_wr0_b 1.927e-04
icc_c_wr1_b 1.932e-04
icc_c_wr2_b 1.932e-04
icc_c_wr3_b 1.932e-04
icc_c_wr4_b 1.958e-04
icc_c_wr5_b 1.964e-04
icc_c_wr6_b 1.964e-04
icc_c_wr7_b 1.979e-04
icc_p_wr0_b 5.789e-03
icc_p_wr1_b 5.872e-03
icc_p_wr2_b 5.889e-03
icc_p_wr3_b 5.928e-03
icc_p_wr4_b 6.185e-03
icc_p_wr5_b 6.356e-03
icc_p_wr6_b 6.530e-03
icc_p_wr7_b 6.601e-03
icc_c_desela 0.000e+00
icc_p_desela 8.948e-05
icc_c_deselb 0.000e+00
icc_p_deselb 1.043e-03
icc_c_peak 6.020455
icc_p_peak 102.321769
icc_c_inrush 3.248879
icc_p_inrush 97.449304

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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_tt_0p90v_0p90v_25c.lib Normal file
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models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1_tt_0p90v_0p90v_25c.ps Normal file
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